If any one thing can be said to represent the Information Age, it would be the Internet. In 1998, the amount of data spilling out of the edge of the network onto the average person's desktop might have equaled a small novel. By 2000-with Internet telephony, live video, unified messaging, global e-commerce and a glut of new applications commonplace-it will equal the Library of Congress.
This explosive growth is compromising the performance capabilities of the network equipment itself.
Because of the tremendous capacity of fiber-optic transmission systems, and the increasing power of microchips, network-equipment designers had been able keep up with the demand. But no longer. Available microprocessors-and their equipment architectures have hit three distinct "performance walls," and their incremental growth in power has been eclipsed by an exponential growth in demand.
This means that while tomorrow's network equipment-routers, switches, ADMs and the like-will look similar to today's equipment on the outside , the internal design will need to be dramatically different.
In the early '90s, the available Mips in reasonably priced processors to do switching, routing, protocol conversion and performance monitoring were surpassed by demand. Engineers responded by using two or more processors-an expensive and software-intensive solution. Various technology companies produced application-specific processors. And for the highest-performance applications, network-equipment manufacturers designed their own ASICs to handle part of the burden-a very expensive concession.
Even with such strategies, available "horsepower" will quickly become inadequate. Based upon the most conservative demand estimates, in 2005, one processor instruction will have to result in the movement of forty times the amount of data through network equipment as it does today. But in the same period, absent a totally new architecture for network processors, processor performance will only improve about 6:1. We call this the "processor wall."
The other two limiting technologies are the buses and average memory access time. By our estimates, the performance of buses-especially the popular and predominant PCI bus-will be eclipsed by the demand throughput in 1999. Bus performance will improve less than 50 percent in the next six years-a far cry from 40:1. This is the "bus wall." Andcurrent shared-memory-access technology will become limiting in about 2002. This is the "memory wall."
A new class of network processor is required to solve those performance and partitioning problems. It must support distributed processing, and complex buffering and queuing mechanisms, and reduce the number of packet transactions over the system bus. A recently introduced category of network processor called the Edge Processor may be just the ticket; it can handle much of the hard work of network equipment. This simple design change may let networks of the 21st century reach their full potential and keep pace with demand.
-Michel Desbard is chief executive officer of T.Sqware Inc. (Santa Clara, Calif.).
