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Quantum computing steps forward at IEDM








EE Times


NEW YORK — Single-electron transistors and other quantum computing topics will be among the most intriguing subjects discussed at this year's International Electron Devices Meeting (IEDM) in San Francisco, Dec. 11-13. An panel session on how single-electron transistors can be applied for both logic and memory functions will be followed by a presentation by NTT Communications describing the first working circuit with single-electron transistors.

In his plenary session, David DiVincenzo, an IBM fellow at the company's T.J. Watson Research Center (Yorktown Heights, N.Y.), will speak on "Prospects for Quantum Computing."

DiVincenzo will detail his company's ongoing research into the ever-deeper throngs of microscopic particles. IBM has employed recent theoretical insights to derive a new formal basis for computation based on the laws of quantum physics.

By making bits that obey the quantum-mechanical principles permitting coherent superpositions of discrete states, efficient algorithms for some otherwise intractable problems like prime factoring become possible, said DiVincenzo.

First steps

Work is just beginning on the physical requirements that the "transistors" of a quantum computer need to satisfy. DiVincenzo will describe several solid-state proposals that are under consideration. The devices being explored have a superficial resemblance to the transistor, in that the switching of a bit is controlled by a gate voltage.

For the most part, however, the devices will be entirely different from any existing one. The bit will be embodied in a single microscopic degree of freedom — for example, in the spin of an individual trapped electron.

The switching of this "transistor" will most resemble a voltage-controlled, pulsed electron spin resonance operation. Almost every basic aspect of the device — initialization of the bit, interaction with neighboring bits, error processes that it might be subjected to, and its readout — has to be thought out and investigated from scratch.

This year's Emerging Technologies session will combine fact delivery with an exchange of opinions and ideas. The intent of this session is to provide solid, unbiased, background technical information and to engage the audience in a discussion of nascent technologies' merits and potentials. This format, as compared to the traditional panel discussion format, allows the audience to learn more information and participate in an extended discussion.

The panel will include researchers from companies such as Fujitsu, IBM, Infineon, Philips and Toshiba, as well as from Cornell and Delft University of Technology.

The Emerging Technologies session will cover two topics: single-electron transistors/devices and alternative memory technologies. The single-electron transistor (SET) has been proposed both as a logic device and a memory element. It utilizes the Coulomb blockade effect and requires a small physical device dimension for operation above cryogenic temperatures. The advent of nanolithography and associated patterning techniques has raised the prospects of incorporating SET into a base CMOS technology.

The session will start with an introduction to SET, summarizing its benefits and potential problems, along with current research trends. An open discussion will follow.

In the second half of the session, speakers will introduce alternative memory technologies. While conventional memory technologies such as the DRAM, SRAM and floating-gate non-volatile memory will continue to scale to even smaller dimensions and higher density, recent development in alternative approaches may cover entirely different application spaces with different read/write speeds, retention and endurance characteristics.

Further discussion

The speakers will give an overview of alternative memory technologies, describing their operating principles and application space. Examples of alternative approaches include ferroelectric memory, magnetic tunnel junction memory, single-electron memory, and nanocrystal floating-gate memory. The overview will be followed again by a discussion with a panel of experts on these technologies.

For its part, NTT's paper will document the travails of its search for single-electron pass-transistor logic. The circuit it plans to present at IEDM consists of two single-electron transistors fabricated on a silicon-on-insulator substrate. The researchers were able to perform basic logic operations including half-sum and carry-out of the half adder at a temperature of 25K. Theirs is the first experimental demonstration of arithmetic operations by single-electron transistors, the NTT researchers claim.

More IEDM coverage.











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