"In the old days, once you had an engineering spec, the yield problem was a manufacturing problem," said Kibarian. "Today, due to process complexity, the yield problem is as much a design problem as it is a manufacturing problem."

Use of third-party intellectual property (IP), while a savior from time-to-market pressures, can also be a key factor affecting IC yield, Kibarian said. "Dataquest said that 75 percent of chip area is going to soon come from sources other than your firm," said Kibarian. "What this means for yield ramping and bringing a product to volume is that you don't necessarily know what is going inside the most detailed level of your design. To get this knowledge means you are going to have to characterize those blocks in detail from a manufacturing perspective, even though the internals aren't really known to you."

Another problem, Kibarian said, is that while the number of processing steps has increased about 10 percent per year, die size has stayed relatively the same. "The difference is that at 0.5 micron that was a three-layer metal and today that sweet spot is six- or seven-metal layer," said Kibarian. "This is another yield loss factor just because you are processing more layers, and the complexity between layout pattern and process causes additional yield loss."

Samples today, volume tomorrow

And while design and process complexity problems are increasing, time-to-volume production of silicon is shrinking, Kibarian said. He noted that while the black and white TV took over 20 years to make it to the one-million-unit sales mark, Sony Playstation 2 hit that mark in only two days. "The time you have to bring a product from sample quantities to millions is basically overnight," said Kibarian.

To effectively deal with these interwoven problems requires a new approach that takes design, process, and manufacturing into account.

Kibarian said that dummy fill is normally used to address the main problems that impact IC yield problems, but that most design houses don't like to use it for high performance designs because it can change capacitance.

"On the manufacturing side you have to quantify what is the impact on the circuit and what is the optimal strategy," said Kibarian. "You can use different dummy fill shapes, ground or not ground them, you can avoid putting them in particular parts of a design."

Key questions to consider relate to the impact of using dummy fill on a design, its impact on the system, and the type of performance needed for the system. "If you have a relatively stable design, then you can probably use dummy fill and make it more manufacturable and not worry about the performance impact," said Kibarian. "On the other hand, if you want high performance you may need to do a more aggressive dummy fill."

Kibarian noted that new 0.18-micron steppers create in-chip, linewidth variation that requires the use of rules or modeled based optical proximity correction tools.

"With these tools you get what you drew," said Kibarian. "This is great from the design side, but from a manufacturer's perspective it creates issues in terms of printability, printability verification and gap-fill issues, which will then create issues for your yield."

Kibarian noted that about 4 percent of a 0.1x transistor's drive current will be variable due to intrinsic doping variations. This means that designers will need to compensate with statistical design by adding more margin into their designs, he said. "From the manufacturing side, you have to rethink the way you characterize technology because designers are just going to need to know more about the technology in order to work with it," said Kibarian.

To take advantage of the large gate counts available today, designers are using more IP, which needs to be characterized for yield, Kibarian said. "When a product doesn't achieve the yield you expected, you have to debug the product yield issue," he said. "You have to figure out if the yield of this core is what it should be, given its implementation in that system."

Kibarian said that users should create — or better yet, IP vendors should provide — black-box yield models characterizing what the yield of that block should be. "That way you have some target when you make the big breakout of your design," he said.

Kibarian also suggested that IP vendors should have their IP characterized for how the cores use a given technology. "The characterization should look at the ranges of density, pattern shapes, etc.," said Kibarian. "This should help users from a design-for-quality standpoint and understand where your yield loss is going to be and where you want to go back and make changes."

Kibarian also suggested manufacturers create a yield-impact matrix to find the best manufacturing configuration for a core.

"This will streamline the design process but may require vendors to implement simple fixes to their IP or even redesign the blocks," said Kibarian.