De Geus called for "a fundamental change in the way we think" about the design process. Rather than set milestones that measure the progress of a project in terms of time, engineers need to set milestones that check key uncertainty parameters. In a presentation titled, "Slap it together and ship it," de Geus defined quality as "no surprises" in a design flow or, more technically, "monotonically decreasing uncertainty over time."

If engineers schedule projects to include periodic checks of key uncertainty parameters, they will be more likely to identify and remedy potential quality issues faster, thus enhancing time-to-market, de Geus argued. "If you are designing for something that is urgent, you are designing for quality to the max," he said.

Time is indeed a collapsing commodity in electronic design today, he noted. While products such as black-and-white televisions took 25 years to ship in volumes of one million units a year, today's DVD players hit the one-million-unit shipping mark in less than one year, he said. "Today suppliers need to commit to a very large volume before they are even sure if the product works," de Geus said.

Better design methodologies are one answer to the problem, according to the Synopsys CEO. Specifically, he said one of the most critical design issues today is timing closure in physical design, which can best be addressed by working on both logic and placement in parallel. Signal integrity is another major issue that engineers should address in the early phase of the initial global routing rather than at the end of the design cycle, he added.

"We are seeing chips in fabrication where people are still trying to debug the crosstalk. That's hopeless," de Geus said.

While de Geus' prescriptions map well with the company's latest EDA product offerings, they also fit with the theme of the conference, the first to address issues of quality in design.

Organizers of the ISQED conference said the event has been two years in the works and is aimed at raising the concept of quality to a higher level. Quality is an issue that needs to be addressed in the front-end of the design process as part of the methodology, rather than at the back-end as a final test phase.

On an upbeat note, de Geus said that the rise of 0.18-micron process technology is helping to rapidly advance the move to system-on-a-chip designs. While only about 12 percent of 0.18-micron designs were systems-level chips last year, as many as 74 percent will be in 2003, he predicted.

At the same time, the EDA industry is poised for a move to the next level in design abstraction with system-level software tools, he added. "We are at the beginning of a major change in productivity," he said.