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RF design tools are bottleneck to some, opportunities for others








EE Times


As RF CMOS integration follows its exponential curve with multiple radios on single chips operating at higher frequencies and with added digital circuitry, the ability of available tools to perform accurate simulations is falling further behind. For those on the design side, this continues to be a bottleneck on the path to higher integration. However, for those on the tool side, it is "the next big thing."

According to Ed Healy, vice president and general manager of the wireless business at Silicon Labs', this is no secret. "For analog design in general, the tools are not as sophisticated as with digital." The result, he said, is that RF is very much hand-crafted design. Healy also lamented the lack of adequate tools for electromagnetic 3D-type simulations. "There are some, but it's very difficult to take a full radio section and fully simulate it." The problem is a lack of convergence, with simulations generally getting hung up mid-cycle. This lack of adequate tools, Healy said, is the reason RF front ends generally go through several revisions of a part.

Dan Mathers, president of IceFyre Semiconductor, concurs with Healy's assessment. "It's a great unexplored frontier and a great way to add value," he said. Most companies now doing RF have large modeling teams to model transistors. Every company is doing it. If someone can eliminate that, it would be a huge benefit to the industry." According to Mathers, Agilent's ADS package represents the state-of-the-art with respect to RF design tools, "but it does depend on the underlying transistor models from the foundries." Healy was more emphatic. "Cadence and Agilent [tools] are inadequate for what we really need, but good first steps. It's clearly an opportunity for someone to address this."

From Agilent's point of view, the level of integration under way today creates a capacity issue. "The needs of the design are outstripping even the PCs and combinations of compute and simulation/analysis improvements," said John Moore, product planning manager of Agilent's Device Modeling Solutions division. "The complexity is mind-boggling."

The issue, as Moore sees it, is integration and higher operating frequencies. "That's what's driving complexity now. A typical wireless radio might have 1,000 non-linear devices [diodes, transistors]. People can handle that-but then add parasitic extraction, which adds a further 10,000 to 15,000 linear components to your netlist, and it swamps the capabilities of the current simulation techniques to solve that problem. Ten years ago, the big issue was inaccurate modeling of parasitics; now it's [the modeling of] substrate crosstalk with digital and RF on the same chip."

Companies like SkyWorks are opting for multichip modules. "People are going to SOI for mature low-cost applications, but for less mature applications and higher performance, I'm seeing more of a move to modules," said Moore. "It's the biggest challenge we face when it comes to higher integration," said Mohy Abdelgany, vice president of RF systems at SkyWorks.

To tackle the simulation issue, Agilent is advocating the use of behavioral models that move up the chain from complex device modeling to component modeling. This shifts the emphasis, said Moore. "Then it becomes about integrating them [components], so now you need good models of what's being connected to you. That's the next level of modeling."











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