Statistical timing analysis is a next-generation timing technology that promises to be far more accurate than today's static-timing analysis (STA) tools-accounting for silicon process variables and giving designers an up-front view of chip yield vs. chip performance.

Researchers say the workhorse STA tools method is too conservative and derives timing based on pessimistic and inaccurate worst-case gate and interconnect models.

This overly conservative static-timing approach chiefly sacrifices performance and promises to become more conservative and sacrifice even more performance as process geometries shrink. Researchers also believe that static tools, even in their conservative approach, simply are not accurate enough-ultimately causing re-spins, which lead to product delays.

A statistical timing tool promises, for example, to allow a given semiconductor company to say to a customer: "Given this performance, on this process we can offer this yield and, thus, this cost."

Therefore, if a customer requires high performance, the statistical timing tool would allow semiconductor companies to predict the yield they will lose and let customers know proactively they will need to pay more for the yield loss given their performance targets.

Conversely, semiconductor companies can use the tool to estimate for customers what happens if they back off on performance to give better yield numbers and reduce costs.

The technology would seemingly be attractive to MPU vendors but extremely attractive to ASIC houses.

With a statistical timing tool, MPU makers would be better able to predict the number of die per wafer that are hitting top performance requirements, as well as the number of lower-performing die on the wafer for better binning estimates.

ASIC vendors would be able to proactively let customers know the best mix of performance and yield for a given ASIC design project, reducing the number of ASICs that don't hit the required speed grade and, as a result, have to be thrown in the garbage-with costs eaten by the ASIC vendor or its customer.

The technology also promises to grow design for manufacturing.

The ultimate goal of the academics working on statistical tools is to bring this predictive technology into the design tool arena, perhaps even the RT level, to let designers start their projects optimized for the right mix of performance, yield and cost.

But to get to this point requires the tools be correlated to new processes and their quirks and die-to-die variations, something foundries don't like to disclose to library vendors let alone EDA companies.