Potential applications of sub-100-nm process technology, which makes possible hundreds of millions of transistors in a single chip, are dazzling. But those semiconductors will never come to be if we don't have the technology to design and verify them in a reasonable period.
As of today, we do not. What we need are not simply new IC design tools, but fundamentally different ways of thinking that will lead to profound shifts in the ways that silicon is designed and verified.
The 2001 International Technology Roadmap for Semiconductors (ITRS) charted an ambitious course for IC device and process technology but carried a stark warning: The cost of design is the greatest threat to continuation of the semiconductor road map. The ITRS also identified a "design productivity gap" in which the number of transistors grows faster than the ability to design them meaningfully.
According to Gary Smith, chief EDA analyst at Gartner Dataquest, this gap really hit home in fall 2002, when "power users" discovered they couldn't even use half of the 100 million gates allowed by 90-nanometer technologies. The result, said Smith, was "panic."
Besides staggering complexity, sub-100 nanometer ICs pose physical design and manufacturing challenges. Several paradigm shifts will be needed to design these ICs. One, according to many observers, is a move from register-transfer level (RTL) to electronic system level (ESL) design.
Other new paradigms are needed so that engineers can verify 100-million gate ICs, create silicon virtual prototypes for "signoff" to ASIC vendors, design for sub-100-nanometer manufacturing and test challenges, and move from isolated point tools to integrated design tool flows.
Even with new approaches and capabilities, ASIC design, as we know it today, will change dramatically. Some electronics OEMs will seek shortcuts or alternatives, such as using programmable or reconfigurable logic, deploying platform-based ICs with pre-defined architectures, or simply putting more functionality in embedded software.
Dataquest's Smith believes that most designers who stick with ASICs will hand 65-nanometer designs over to ASIC vendors at the RTL, rather than synthesizing a gate-level netlist, as they do today. That's because the design for manufacturability issues will be too daunting for all but ASIC vendors and the most sophisticated power users.
The move from RTL to ESL
In the late 1980s, the transition from gate-level design to RTL design marked a turning point for the semiconductor industry. Ever since, EDA vendors have been trying to bring chip designers to the next highest level of abstraction, now called ESL. At this level, designs start with no notion of architecture, go through hardware/software partitioning, and are ultimately refined to the register-transfer level.
ESL hasn't been a big success, but many ob-servers think its time has come. "The crisis of complexity hit, and now all of the power users are de-manding ESL tools," says Smith. What ESL will allow, he said, is design with large, reusable intellectual property blocks.
"At 100 nm or below, the RTL flow will break down, forcing an elevation to a methodology based on design entry at a higher level of abstraction-the new ESL design paradigm," says Jacob Jacobsson, the president and CEO of Forte Design Systems.
Dataquest describes an ESL flow in which designers use behavioral design entry, simulation, ESL co-verification, and "interface synthesis" to assist with hardware/software partitioning. Next comes architectural design, which includes behavioral synthesis, a lower level of co-verification, and power and test planning. The end result is an RTL design.
Many people think verification is what's driving ESL. Many chip designers will take their first steps beyond RTL with the emerging SystemVerilog language, which includes some C language constructs, and some are moving further upstream to use SystemC for its fast simulation speeds.
"The verification task involves hardware and software. We need to not only verify both hardware and software working together, but move stuff back and forth between hardware and software to play what-if games with architectures," says Wally Rhines, Mentor Graphics CEO. "It's one level up from what the industry has been doing, and it changes the design paradigm substantially."
Since verification already can take up to 70 percent of the IC design cycle, it's been an area of emphasis for dozens of EDA vendors. A huge array of new tools and technologies has emerged, including formal equivalency checkers, property checkers, assertion-based verification, simulation-based formal techniques, and coverage and debugging utilities. But new thinking, not just new tools, is needed for the verification of sub-100 nanometer ICs.
One new concept is "design for verification," the idea that design engineers will plan for verification as well as for synthesis and layout. It's critical, says Aart de Geus, Synopsys CEO, because chips are becoming too complex for engineers to simply throw designs "over the wall" for verification teams to verify.
From dynamic to static
One aspect of design for verification, De Geus said, is the move from dynamic techniques, such as simulation, to static, formal approaches that can handle much larger capacities. Another aspect is the automation of random testing via directed coverage algorithms. De Geus views the SystemVerilog language as a critical linchpin for design for verification, because it preserves existing investments in the Verilog language while adding new constructs for capturing intent and specifying properties and assertions.
Harry Foster, chief methodologist at startup Jasper Design Automation, has called for "property-based design," in which designers will use formal properties to specify design intent. Multiple tools-synthesis, testbench generation, simulation and formal verification-will run off the same properties, he believes.
Beyond design for verification lies another challenge: the automation of RTL functional verification. This, says Smith, will take place with the emerging "intelligent test bench," which partitions designs into blocks for verification, assigns tools, and runs the appropriate tools on the appropriate blocks. Indeed, EDA vendors are beginning to offer unified verification environments that serve multiple design domains, and levels of abstraction, with both dynamic and static tools.
Following the completion of RTL design and verification, the next step traditionally would be logic or physical synthesis, producing a gate-level netlist and perhaps a placement. But for sub-100 nanometer ICs, the next step may be the creation of a silicon virtual prototype. This is an RTL representation of the design that provides not only floorplanning but also estimates of power, timing, and area, with knowledge of the targeted process.
Silicon virtual prototype
"Silicon virtual prototyping will provide the planning capabilities needed to accurately predict the characteristics of the final implementation far in advance of the completion of the chip," says Dave Reed, vice president of marketing at Monterey Design Systems.
Dataquest's Smith thinks ASIC designers will divide into two camps at 65 nm. Mainstream users will build a silicon virtual prototype and turn over RTL designs to ASIC vendors for implementation. "They're seeing all the problems they'll have at 65 nm and saying they don't want any part of it," he said. Only power users, according to Smith, will continue with synthesis, placement and routing.
Lavi Lev, general manager of Cadence's implementation division, sees two parts to the silicon virtual prototype. One is physical prototyping, which exists today. Another is quick synthesis, which needs to be blended with physical prototyping to obtain accurate timing, area and power estimates. It may also be possible to get an early view of nanometer effects, such as voltage drop, he noted.
"I believe prototyping needs to be part of a silicon compiler solution," said Rajeev Madhavan, CEO of Magma Design Automation. Silicon compilation is a concept that was introduced in the mid-1980s, but never really adopted. Madhavan believes the key to sub-100-nm chip design is the emergence of new "silicon compilers" that can take an RTL description and automatically generate the GDSII files used to produce photomasks.
Manufacturability task
Those "power users" who go through the entire IC implementation cycle will face a host of issues with sub-100 nm designs. These include silicon effects such as voltage drop, crosstalk noise, leakage current and inductance. Power management will become a much more serious concern. But what worries many design teams most is manufacturability.
Designers are already starting to use resolution enhancement technologies (RETs), such as optical proximity correction (OPC), on selected photomask layers, in order to force photolithography equipment to print correct features on chips at 130 nanometers and below, where feature sizes are smaller than the wavelength of light used to create them. Below 100 nm, RET will be needed on far more layers, noted Mentor's Rhines.
At 90 and 65 nm, other issues will emerge. There will be considerably more process variability as feature sizes shrink, a factor in obtaining acceptable yields. Statistical timing analysis will predict yield distributions as well as timing, forcing designers to understand process effects.
Copper interconnect and chemical metal polishing (CMP) also raise a host of problems, said Charlie Huang, vice president of business development at Cadence; for example, copper wires have variable heights and therefore may exhibit unexpected resistances and capacitances.
One consequence of manufacturing issues, noted Dataquest's Smith, is that current approaches to design-for-test fall apart. One consequence is that the traditional "stuck at" fault model is no longer adequate. Designers must look at transition faults caused by resistive vias, and metal bridging faults. At-speed, delay fault testing will be needed. What all this means, said Rhines, is many more test vectors.
Integrated flows
A final paradigm shift that's crucial for sub-100 nm designs is point tools to integrated design systems. The 2001 ITRS speaks of the need to move from a traditional "waterfall" design flow, consisting of discrete steps, to an integrated system in which logical and physical tools can operate together. What's needed, the document states, is a modular open architecture with an industry-standard interface for data.
That's exactly what the user-backed OpenAccess Coalition is trying to achieve. With an industry standard API and data model, based on the OpenAccess database created by Cadence, design tools can exchange data in shared memory. This allows, for example, routing to work closely with signal integrity analysis, even with tools from different vendors.
But it's unclear whether other EDA vendors will embrace this effort. Synopsys, for example, has opened access to its own Milkyway database. Magma and Monterey have both created integrated RTL-to-GDSII design flows based on their own databases.
One of the most ambitious ideas behind OpenAccess is its possible extension into manufacturing. As of now, mask shops have no information about design intent; they only receive geometric data. Providing more intelligent data could save the billions in mask costs, some observers say. It's possible that the emergence of a common data infrastructure for both design and manufacturing will be the biggest sub-100 nm paradigm shift of all.
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