Solutions will come, but probably not as fast as needed to keep CMOS performance and power consumption improvements on the schedule established by the International Technology Roadmap for Semiconductors (ITRS). And while some companies will face Darwinian extinction, others will survive by making the right material and integration choices. Still others will take a different path and fail, or merge with the survivors.

One thing is sure: CMOS must change, and fast.

The likely timing of the key innovations needed for high-performance logic is next year for "technology boosters" like strained silicon, and 2007 for high-k gate dielectrics and metal gate electrodes. By 2008, fully depleted silicon-on-insulator may come in, followed shortly thereafter by multi-gate device structures such as FinFETs.

Something like that progression needs to happen to follow the curve of Moore's Law.

Each company, of course, is likely to take a unique path, depending on its own products and technology decisions.

Peter Zeitzoff, a senior fellow at International Sematech and co-chair of the ITRS PIDs (process integration, devices, and structures) technology working group, says, "If you look at transistor performance over the history of the industry, there has been a 17-percent-a-year improvement. We can't stay on that curve much longer without technology boosters."

Hans Stork, a senior vice president at Texas Instruments in charge of silicon technology development, asks the key real-world questions: "Can we stay on a 70 percent shrink cycle (every two years)? That depends on whether new materials deliver the expected benefits, if we use them. From a physics point of view, it may be possible. But I'm not sure if we can change the slope of new materials introduction that drastically."

For an industry experiencing a slowdown in revenue growth, costs and yields are of rising importance, he said.

"The devil is in the details. Can the industry add these new materials in such rapid succession on devices with 20-30 nanometer gate lengths? And build billions of them on the same chip at decent yields?" Stork asked.

Dave Robertson frames the problem a bit differently. "All the rules are changing. At 180-nm or even 150-nm design rules, when you turned the device off, it was off. As we go to 130-nm, even when you turn it off, it isn't really off," said Robertson, a director at Analog Devices Inc. in charge of designing high-speed converters.

Silicon-on-insulator (SOI) has been one way to limit leakage at the junctions of the source and drain. IBM and Motorola Inc. have boosted performance of their PowerPC microprocessors with SOI by reducing the amount of capacitance on the device. But getting control of leakage at the gate appears to be a much more difficult challenge, one that will require moving beyond the stable marriage of silicon and silicon dioxide.

Unfortunately, progress thus far does not look good, and a high-k material may not be ready for the 65-nm node. Some of the best material scientists in the world have been working on high-k "for a long time," said IBM's Welser, "and there are still some things holding us up."

Most of the metal oxides, such as hafnium oxide and others, seriously degrade mobility in the channel. That may be dealt with by using strained silicon to boost mobility.

More troubling than mobility, said Joe Mogab, director of Motorola's advanced products research and development lab (APRDL), is setting the threshold voltage (Vt) and keeping it there. When devices with high-k oxides are created, the Vt can jump to 500-mV or more-higher than the 200-300 mV needed for logic chips.

And when the chip goes into operation and heats up, the Vt can move around unpredictably.

"We think there are ways around the so-called mobility problem," Mogab said. "The biggest problem is the threshold voltage, not just the variation or instability, but the absolute value of the threshold voltage is too high. We're making progress, but we're not there yet. Threshold voltage is what it's all about. You either get it right or you're out of business. There's no compromise."

Soitec materials stack combines strained silicon and silicon-on-insulator to improve performance.

When high-k dielectrics- often called metal oxides-are introduced, the threshold voltage can be asymmetric between the PMOS and NMOS devices.

"It really is scary. The degree of difficulty is compounded by the fact that you have two channels, and they are not always synchronized in their ability to take on new technology. But you can't walk away from CMOS-it is so good in terms of quiescent power," said Mogab.

Some companies, such as Advanced Micro Devices, argue that performance can be increased by bringing in metal electrodes, even before a high-k oxide is introduced. AMD is promoting a fully silicided approach, in which the polysilicon is completely replaced by a midrange bandgap metal.

Others plan to introduce a high-k material first, then bring in metal gates at the next node to reduce risk.

Motorola is in a third camp, which believes that a double jump will be needed, bringing in metal gates at the same time as the high-k oxide.

"We think that's a must," says Mogab. "We really don't have a choice," because of the reaction between the polysilicon and the high-k oxides. We don't believe poly will be made to work" with the metal oxides, he says, adding that "there may be some Band-Aid approach, doing some capping layer over the metal oxide in order to buffer it from the poly. That is going to be a huge problem for extendibility, because whatever you do there will hurt you in terms of the effective dielectric constant."

'We're still struggling' with high-k oxides. Joe Mogab, Motorola

Companies such as France's Soitec and several large wafer suppliers in Japan are readying a layer transfer technology that will deliver strained silicon on SOI. In that way, strain can be introduced across the entire wafer.

Or strain can be introduced to the channel region during the process flow, through in situ local epitaxial deposition.

Most of the discussion of strained silicon involves the tensile strain caused when a top layer of silicon is deposited on top of a graded layer of silicon germanium, with 20 percent or more germanium content. The larger germanium atoms stretch the smaller silicon lattice, improving mobility of the electrons in NMOS devices considerably.

PMOS devices are less amenable to improvement from tensile strain, but it has long been known that PMOS transistors speed up when under compressive stress. Some companies are working on improving both the tensile and compressive strain, a difficult challenge.

Howard Huff, a senior fellow at Sematech, says, "Once you start talking about strained silicon, there is a whole lot more complexity there. And when you combine strain with SOI, you have to have very thin layers, and there are costs involved, depending on how you make the structure."

'You have to think four moves down the line.' Suresh Venkatesan, Motorola

When ultra-thin-body, fully depleted structures are brought in, the silicon body thickness should be less than 200 Angstroms, which scales to 100 Angstroms by the end of the ITRS road map, Sematech's Zeitzoff said. That presents a high set of standards for the wafer vendors, and equally daunting challenges to metrology vendors.

Intel appears to be first to the starting gate, with a form of strained silicon coming to market next year in its 90-nm microprocessors. Motorola plans to introduce some form of strained silicon in its later-generation 90-nm process, coming to market in 2005. IBM plans to combine strained silicon with SOI at the 65-nm node. Texas Instruments is on a similar schedule.

W.T. Shiau, director of the advanced device development department at United Microelectronics Corp. (UMC; Hsinchu, Taiwan), said UMC's study of strained silicon showed a 10 percent speed enhancement at the same active power. However, Shiao says, "There are several major issues, particularly the introduction of defects" in the silicon. Thermal budgets must be controlled carefully in order to limit the number of defects and maintain the level of strain throughout the process cycles, he said.

The decisions being made now about strained silicon must be thought out with further materials and device structures in mind. That is why the uncertainty over the availability of a high-k oxide is so agonizing for technology managers. If a high-k material, or even a "mid-k" material such as hafnium silicate, can be brought in to control leakage current and support device scaling, then planar CMOS structures probably can be extended for several more generations.

But some believe the high-k introduction will prove so intractable that vertical device structures, such as FinFETs, may be needed earlier than ever imagined just a short time ago.

FinFETs replace the planar stack with a vertical channel and a gate on each side. The dual-gate structure allows more current to be driven through the channel, while keeping the gate oxide at somewhat thicker dimensions. A 25-Angstrom gate oxide thickness on a FinFET might resemble the performance of a planar structure with a 15-Angstrom thickness, for example.

However, FinFETs only forestall the need for a high-k gate oxide by a generation or two. And for an industry in which all of the EDA layout tools and product designs are based on planar structures, moving to FinFETs is a non-trivial step. Dual-gate transistors can be combined with planar transistors on the same chip, and IBM already has demonstrated SRAM cells and ring oscillator circuits made from FinFETs, said Meikei Ieong, a research manager at IBM's T.J. Watson Research Center.

The advantage of FinFETs is that with the higher aspect ratio and dual-gate structure, devices can have a higher current density per unit area. Ieong notes that a FinFET is still a MOSFET, and one in which the drive current can be varied simply by putting two or even three fins on one transistor. FinFETs enable good control of the channel and support much better threshold voltage control, at very small device dimensions, than planar transistors.

Nevertheless, Ieong said bringing in FinFETs will be a major business shift for an industry with layout tooling and design skills based entirely on planar transistors. Ideally, high-k will come in before FinFETs, Ieong said.

But again, the gating item of high-k arises.

"Will high-k ever happen? We don't know. There isn't much progress. But perhaps there is enough research going on that a high-k can be brought in faster than people now think," Ieong says.

UMC's Shiao said his company has made FinFET-based circuits and has found that "alignment of the lithography steps is the major challenge. We didn't focus on making the smallest possible devices-our test vehicle has a channel of less than 40 nm. But we believe close control of the alignment will be an issue facing the industry."

Suresh Venkatesan, director of CMOS platform development at Motorola, said that even if FinFETs are brought in at the 45-nm node or later, technology managers must think ahead to how the decisions they make now, about strained silicon, gate oxides, and so on, might combine with the dual-gate structures that surely will be needed someday.

"What is the right progression out from here? You can't do something now, and then go swap everything around (at a later node). You have to have a road map that allows you to build," technology generation by technology generation.

Indeed, Venkatesan said when thinking ahead to 3-D structure, "some of these techniques the industry is contemplating now don't translate very well to vertical structures. There must be an evaluation of the progression of technology. You have to think four moves down the line" in the chess match of semiconductor scaling.

But again, the question of when a high-k gate oxide looms over all those decisions.

"The key to that progression," Venkatesan said, "depends on availability of an alternate gate stack. Even if you choose to go in the direction of FinFETs, you could gain a generation or two, but then you need to choose to scale that oxide thickness, and then guess what? You are back to needing a high-k."