As semiconductor processes move to 0.13 micron, design costs are skyrocketing. The traditional approach to chip design, standard cell, is increasingly uneconomical. Industry estimates for the cost of an average chip design in 0.13 µm is now around $10 million just to get to the first production unit. Thus, with a 50 percent gross margin and $50 average selling price, that's 400,000 units sold before the first dollar of real profit.

Structured ASICs are emerging as the design solution that addresses this and other IC cost problems, without sacrificing performance or density. A structured ASIC has most of its fabrication and metal layers predefined. This approach simplifies the back-end EDA flow and significantly reduces nonrecurring engineering costs because only a few custom masks are needed. The combined savings are substantial; using a structured ASIC takes the cost of a 0.13-µm design down from $10 million to around $3 million. Unit costs are kept low, because the die is identical for all users for most layers. Wafers can be pre-fabricated and banked for final customization, giving volume price breaks to everyone.

While this sounds a lot like the old gate array approach, there are significant differences. In gate arrays, the building block is primitive and all metal and via layers must be customized. Structured arrays use a more complex building block — the module — and only two or three layers are customized. Despite the module's complexity, structured-ASIC designers write standard Verilog or VHDL and use traditional synthesis tools &$151; exactly the same front-end EDA flow that they have been using for years. The modules already have solved many of the timing and performance issues that plague gate-level design, so back-end EDA flow progresses more rapidly and with less risk than the gate array or standard-cell approach.

This rapid, reliable design process provides another benefit. Structured ASICs speed time-to-market, reducing design time by as much as nine months. Most of the design is already complete and verified and fab cycles are significantly faster. Beating the competition to market by nine months is a staggering advantage. While it is impossible to quantify the dollar value of this benefit, it is clearly huge. Imagine if your competition beat you to market by nine months.

The value of the structured-ASIC approach is being proven in the market today. Lightspeed's third-generation products are being built for myriad system and semiconductor customers. Further, competitive offerings from companies like AMIS, Fujitsu, LSI Logic, and NEC have validated the structured-ASIC marketplace. Ultimately, we believe that structured ASICs will become the standard ASIC design method for most of the industry.