While all industries have been affected by this most recent economic downturn, design automation has weathered the cyclical nature of the electronics industry many times before. Consider some of the impressive innovations that have been taking place in the area of electronic system-level (ESL) design or, more specifically, ESL verification.

The concept of ESL design has been discussed for several years but has never gained real momentum. In theory, ESL design would give chip designers the ability to design with a top-down approach-from system to chip-raising the level of abstraction to the architectural level at which they initially imagine and create their designs, enabling the earliest possible integration of software and hardware after partitioning at the system level.

So, why has ESL design not come to fruition? Gartner Dataquest recently identified one possible reason when it said that verification would be the impetus to ESL design. For ESL design to be truly effective, all engineers-system, hardware, software and verification-must be able to verify hardware and software concurrently. Until recently, no tools existed to accomplish that. Most verification systems require specialists to operate in an isolated environment and focus exclusively on the needs of verification engineers, at the exclusion of system, hardware and software designers.

Fortunately, even in the midst of our economic woes, Axis has been working hard to remove these roadblocks, creating a totally new paradigm, Design Team Emulation, to open verification to all designers and merge the previously disparate worlds of software and hardware verification. New verification systems developed with this concept are easy to use and allow quick debugging at higher levels to address the validation of system diagnostics, device drivers, RTOS and application software. They are single-kernel-based, combining simulation/acceleration/emulation systems with a single unified database. The best of this breed are event-based, rather than cycle-based, which is more akin to the design tools used to create system-on-chip designs. This reduces verification cycles and creates cost-effective and reliable designs that resolve the challenges associated with SoCs at lower geometries.

Electronic companies have concluded that software is the key differentiator for their embedded, consumer products. Therefore, verifying software and hardware concurrently using a top-down system-level methodology is a must to achieve cost savings and profitability with these increasingly complex chips.