After a decade of trials and false starts, the transition to 300-mm wafers is moving to a new phase, one in which the early adopters expect to gain significant competitive advantages over companies still in the wait-and-see mode.

With the industry in a downturn marked by weak demand, many companies have no need for more capacity, least of all a multibillion-dollar 300-mm fab. But the economic reasons that drove the chip industry to switch from 4- to 6- to 8-inch wafers are here again, according to the early adopters.

Ritchie, the manager of TI's DMOS 6 fab, said, "Internally on logic, we are trying to spend all of our capital on 300 mm. We're clearly at the point where 300 mm is much more cost-effective today than buying new 200-mm tools. I believe that with a few more months under our belts, we should be seeing 30 percent cost improvements by the middle of this year."

Texas Instruments had been averaging 10,000 monthly starts for 300-mm wafers at DMOS6 this year, and expected to realize an actual output of 10,000 by this month, initially at 130-nm design rules. Intel is running slightly fewer wafers now at 130-nm rules, but will increase sharply once 90-nm manufacturing begins in a few months.

By year's end, IBM may be running 15,000 to 18,000 of the 300-mm wafers per month, filling its first module at Fishkill as part of its emphasis on high-end foundry manufacturing. "IBM has always been recognized as a technology leader, but this is the first time we have that, and have the capacity," Davari said.

There is plenty of 300-mm manufacturing activity beyond America's shores. Toshiba Corp. is building two 300-mm fabs, the first opening next year at Oita, Japan, for system-on-chip-type logic chips. The second will ramp up in 2006 at Yokkaichi, Japan, for flash memories. Samsung Electronics Corp. is building its DRAM fab first, then equipping a logic shell for system-level-integration devices in South Korea.

Taiwan Semiconductor Manufacturing Co. is running about 5,600 of the 300-mm wafers per month now at its Fab 12 in Hsinchu, Taiwan. Normalized to 200-mm wafers, TSMC is processing a total of 356,000 wafers per month, of which a relatively small proportion, about 14,000, comes from 300-mm production.

United Microelectronics Corp., which built one of the earlier 300-mm fabs in Japan with Hitachi Ltd. as its joint-venture partner, is running about 5,000 of the 300-mm wafers per month at its fab 12A. UMC plans to begin pilot production in the middle of this year at its joint venture, UMCi, with Infineon Technologies AG, the Munich-based company that did pioneering work with Motorola Inc. at a 300-mm development fab in Dresden, Germany.

Joel Monnier, director of research and development at STMicroelectronics (Geneva), said the Crolles2 300-mm development fab-part of ST's alliance with Philips Semiconductors and Motorola-is now being equipped. By 2005, the partners expect to have invested $1.4 billion at Crolles2, and to have reached moderate volumes: about 10,000 wafers per month, split equally among the three partners. "We will achieve very, very short cycle times at Crolles2," Monnier said. By using single-wafer processing, the partners expect to achieve a turnaround time of 0.35 day per mask layer.

ST has a 300-mm manufacturing site planned for Sicily, and Monnier said the company is studying when to move forward with 300-mm production there. "The types of markets we are in may need that less quickly than DRAMs or microprocessors," he said.

For IBM, Intel and others, the movement to 300-mm wafers is linked to the transition to 90-nm design rules. Intel and IBM will do virtually all of their 90-nm commercial production on 300-mm wafers.

Asked to rank the major challenges brought by 300-mm wafers, Ritchie listed several: process integration, process uniformity across the wafer and overall tool maturity. He noted that some issues are "in the technology basket" and thus are related to such concerns as bringing up copper interconnects and 90-nm design rules on 300-mm wafers.

A 300-mm wafer will deliver a 30 percent cost advantage over 200-mm wafers.

Asked if factory automation, particularly the wafer transport system required to move the heavier wafers, has been a big problem, Ritchie said, "Where we are to date, automation doesn't make the list. If I need 10 more people to handle the wafers, it's not costing me [productivity] because we are not at the point of running 30k wafers a month, we are at the point of reaching process maturity on a new tool set. We can overcome wafer transport issues with a sneaker net."

The biggest challenge has been bringing up copper. "Any time you change metal systems once in 20 years, it's a learning process," Ritchie said, pointing to the polishing of copper interconnects as a continuing issue. Corrosion control and dealing with stress migration-in which the copper molecules move at the point where a via makes a connection to the copper line-have presented challenges. "Achieving the right film quality means the plasma fields have to be uniform over the 12 inches-actually, more than that. Uniformity of the deposition, CMP and plasma etch steps have to be controlled over the whole wafer," Ritchie said.

This summer, after initial work at its Kilby development center, TI will qualify its second-phase 130-nm process at the DMOS 6 fab, with the Corel low-k dielectric. Low-k will be used across the board at 90-nm design rules by all the major manufacturers, and polishing on the porous low-k materials promises to be difficult.

Intel is making a bold move, putting all of its 90-nm eggs in its 300-mm baskets. Its D1C development fab in Hillsboro, Ore., brought up the 90-nm process on 300-mm wafers, and will be converted to high-volume manufacturing when D1D takes over development of the 65-nm node. D1D, also in Hillsboro, is now being equipped with tools; 65-nm prototyping starts there next year.

After Rio Rancho switches to 90-nm design rules and begins to ramp 300-mm fabrication to volumes, Intel will turn to D1C and to Fab 24 in Leixlip, Ireland, scheduled to come online in the first half of 2004. Then, Intel will convert Fab 12 in Chandler, Ariz., to 300-mm wafers. Construction at Chandler begins in the first half of 2004, with 300-mm production scheduled to begin in the second half of 2005 on the 65-nm node, an Intel spokesman said. "Our objective with 300-mm manufacturing is to reach a 30 percent cost advantage," said Sohn, the Rio Rancho fab manager, "and we are on plan to do so."

The 300-mm generation presents the chip manufacturers with an opportunity to "really automate a factory," Sohn said, with no carts, no lifting and "no half steps." Automation will result in better up-time, improved inventory management, less contamination and shorter cycle times. Intel has been working on advanced process control for the past decade and has found that feedback from one tool can be used to adjust the process of the next tool-a powerful, and necessary, advancement as line widths become ever tighter, Sohn said.