When designers today use the phrase "test IP," they typically are referring to the information necessary to test a particular block. But gradually the term is taking on a second meaning: intellectual property that will be implemented as actual hardware on the chip to help with testing.
The earliest example of this sort of IP is in the embedded-memory business. Companies like Virage Logic Corp. have been active in developing parameterizable built-in self-test hardware that is created as a part of their memory blocks. In some cases, where the size of memory arrays is getting large enough to create yield concerns, this IP may include not only BIST circuitry but also diagnostic circuitry and even switch or fuse arrays to insert redundant bits or rows into a failing array.
The future looks even more interesting. As signals get faster, the possibility of getting a signal off the die and into the circuitry of a tester becomes dimmer and dimmer. Already in some cases the tester pin would place a disabling load on the circuit, assuming there was any way to probe the net in question. So some test engineers are talking about the creation of logic analyzer or oscilloscope blocks that would be included in the system-on-chip. During the test process — and even during power-up calibration — analog switches would route critical signals to these blocks for measurement. This is probably the only way to actually look at signal integrity within the die for diagnostic purposes.
With increasing transistor budgets and increasingly complex on-chip blocks and buses, the future holds a lot more of these ideas. Communications designers are discussing on-chip protocol analyzers to capture the activity on an incoming bus in a comprehensible way. Similarly, complex IP blocks can be equipped with internal state analyzers and even state history buffers — as some microprocessor cores are today — so that an external device can follow the state of a block, set break points and extract real-time traces without having to probe the block.
It is entirely possible that such blocks will become a separate segment of the IP market, just as test automation and design-for-test tools have become separate portions of the EDA market. This would greatly expand a chip designer's ability to record and diagnose events within the silicon. But, ironically, it would create yet another source of IP to be somehow folded into the chip's test strategy.
