Feeling the heat of Moore's Law, companies are feverishly chipping away at shrinking transistors while enhancing performance and speed, as well as reducing power consumption. Among the primary challenges facing designers is finding a more scalable insulating material to replace the venerable silicon dioxide, used for more than 40 years as a gate dielectric.

So far, hafnium oxide has emerged as a leading contender, followed by zirconium oxide. Both materials would allow manufacturers to work with a thicker, more manageable oxide layer on silicon wafers with deep submicron devices. Because of the materials' high dielectric constant characteristics, they exhibit an equivalent oxide thickness (EOT) that is lower than the actual thickness, thereby boosting capacitance while reducing leakage current, a key goal in low power mobile applications.

But the new material does impose some challenges. One of the top problems facing researchers is bringing the electron mobility of hafnium dioxide in line with that of silicon dioxide. Another hurdle is the long-term reliability of hafnium dioxide, which can be further degraded by boron penetration during the gate doping process.

Avoiding the traps

Researchers at UT Austin, led by professor Jack Lee, are waging a systematic assault against these barriers and have scored early, limited success on a few fronts. In an interview with EE Times, Lee said the transition from silicon dioxide to hafnium dioxide does have some obstacles that need to be overcome if high-k dielectrics are to find use at the 90-nanometer node. "One of the potential problems with laying down hafnium oxide is figuring out a good interface," he said. "If one is not careful, you can have charge traps at the interface or in the oxide."

With charge trapping, the voltage applied at the gate is instead absorbed in the "traps" that mine the channel. "That degrades transistor performance by reducing the gain and causing delay," Lee said.

His team tackled the problem by incorporating nitrogen in the hafnium dioxide gate dielectric and by high-temperature forming gas anneal, which increase electron mobility while reducing the boron penetration of the gate oxide that would change the device's characteristics and potentially shorten the oxide's lifetime. That has allowed them to achieve an ultrathin equivalent oxide thickness of 0.7 nanometers, outpacing the International Technology Roadmap for Semiconductors, which calls for a 0.9- to 1.4-nanometer thickness range at the 90-nanometer node.

Lee's team experimented with putting the nitride layer at the interface of the silicon and hafnium. That led to charge trapping, as well as hysteresis — or memory effect — both of which cause a shift in threshold voltage and lower mobility. With nitrogen incorporation on top, however, oxygen diffusion into the gate dielectric was reduced and that reduced the EOT. It also blocked boron penetration.

That said, there are still problems. "Even though we have reduced the traps with the top nitrogen-incorporated layer, we still need more significant reductions to increase mobility." Even with a 0.7-nanometer thin gate oxide, mobility is still too low compared to silicon dioxide, he said.

To boost capacitance, the team has tried a hydrogen-based forming gas anneal at temperatures ranging from 500°C to 600°C, rather than the standard 400°. That yielded "substantial improvements" in rooting out traps in the dielectrics and therefore increased the mobility. Lee's group is currently studying the long-term reliability of these forming gas-annealed devices.

Using hydrogen reduces the charge traps because the hydrogen fills dangling bonds at the interfacial layer and in the dielectric. "The problem is that the silicon hydrogen bond is not a very strong bond," Lee said. "So even though it is a good agent to passivate the bond, it might be a problem in the long-term. If I stress the device, the bond might break again. More study is needed, but the preliminary data shows that the reliability is good."