The bumpless buildup layer (BBUL) package is intended to replace conventional flip-chip technology as a way to overcome some of the interconnect, power dissipation, speed and power-delivery problems that threaten processors as they get faster and denser. Intel plans to deploy the packages by 2006 or 2007, when it expects its processors to contain 1 billion transistors and run at 20 GHz.

Moreover, the technology will give Intel a platform for PC-on-a-package, a potentially low-cost alternative to the system-on-chip.

The approach borrows loosely from ideas broached in packaging and pc-board disciplines. "What Intel has done is taken a variety of packaging concepts that have been looked at a little bit and combined them. I don't think anyone has done this kind of combination," said Jim Walker, principal analyst with Gartner Dataquest. "By putting the die into a pocket and building up the layers, they've really minimized the parasitics and signal delay and increased the efficiency of the processor die."

Rather than fasten the CPU to a bed of solder bumps that connects to the packaging interconnect, the bumpless buildup technique embeds the chip within the organic substrate itself, allowing the whole package to be thinner than a dime. That not only makes the package more mechanically sound but bestows much better electrical characteristics, Intel claims.

Bringing the processor into the package gets rid of the top interconnect layer as well as the C4 solder bumps that normally connect the chip to a flip-chip package. Those have been fixtures of the low-inductance flip-chip package technology since it was invented by IBM in the '60s.

Instead, the bumpless buildup layer connects the on-chip interconnect bond pads with a copper metal layer that is "grown" just like any other layer, thus avoiding the added processing step involved with solder bumps. In that sense, the interconnect looks and acts more like a via.

The result is a much shorter interconnect from the die to the pins, reducing inductance by two-thirds, according to Intel. That is key to preventing the processor performance from being bogged down by signals coming on and off the package.

Signal delay has been a major source of concern since the Pentium II days and has prompted the company to closely align its processor architecture team with its packaging crew. Indeed, it has gotten to the point where overlooking packaging would be as harmful as skimping on transistor, interconnect or lithography technology, said Koushik Banerjee, technical adviser for Intel's assembly technology development group.

"It would be like putting a Formula One engine in a compact car," he said. "We have the silicon and packaging guys working as one team. We do the simulations and timing budgets and give feedback to the silicon guys, and sometimes they have to move around functional blocks to meet timing."

Noise factor

The advantages of the bumpless approach are said to extend beyond performance. The thinner profile also reduces the distance between the processor and bank of capacitors affixed to the base of the package. Those capacitors play a key role in filtering out noise coming on and off the device. The noise factor tends to worsen as power supply voltage decreases. If the filtering mechanism isn't sufficient it can lead to a phenomenon known as voltage droop, whereby the signal noise interferes with the off state of a transistor and makes it indistinguishable from the on state. It is thus crucial to deliver power to the transistors with less delay as clock frequencies scale upward.

"If you place the capacitors close to the die, it will make it that much quicker to power up," Banerjee said. "That's why capacitor placement is so important."

By getting rid of the bumps, Intel also expects to find an avenue to making tighter interconnects to keep pace with higher transistor density. Today a flip-chip can have more than 5,000 bumps, and that count is expected to double in five years. That brings into question the reliability of the solder bumps, which must be precisely placed and held fast by an underfill resin. As the bumps are brought closer together to accommodate more I/O, the danger rises that they will attract each other and cause shorts. The risk becomes greater if the underfill fails to seep into every nook and cranny, creating air pockets that render the joints unstable.

"There's a real problem in flip-chip and ball-grid array [assembly] because the underfill has to wiggle in between by capillary action, and there are chances of 'voids' occurring," said Walker.

Another side benefit to eliminating bumps is that doing so eliminates the lead solder and thus addresses environmental concerns, Walker said.

Moreover, the Intel package should help draw heat from the processor and thus address another major source of concern in microprocessor design. Because the chip is embedded in the packaging substrate, the entire top surface is available to hold a larger heat sink.

Bumpless buildup layer technology is loosely related to a newer board-manufacturing technique that builds up layers of dielectric material and plated copper interconnect rather than stripping away layers, as is more common.

One step further

BBUL takes conventional buildup packaging techniques a step further by boring out a cavity for the die, holding the chip in place with a carrier tape so it is flush with the top layer and then filling in the cavity around the edges with an adhesive.

While the idea of embedding a chip in a pc board isn't new, it previously has not been proposed for anything as sophisticated as a microprocessor, Walker said.

Intel's Banerjee said more work needs to be done to create photomasks for BBUL packages before the technology is ready for practical application. On the business side, the company is weighing whether to keep the patented packaging technology in-house or license it to other chip makers.

Although Intel ships in high enough volumes to influence makers of substrate materials, Walker said it would behoove the company to license the technology as a way to lower the cost of the substrates. "If they could proliferate it and get royalties, they should do that," he said.

BBUL is not only intended to improve the signal integrity of monolithic processors; it also brings within reach the prospect of a PC-in-a-package. Intel and other semiconductor makers are already accustomed to stacking chips such as flash and SRAM, but because of heat concerns stacking has not been practical for PC subsystems.

With BBUL, a CPU, graphics chip, chip set and RAM could be laid out side by side. Further work would be required to overcome the thermal issues of burying so many hot chips in a single substrate.

But combining components on one package could end up being less expensive than a system-on-chip solution because the yields of individual chips are greater than those of a larger all-in-one device, Intel believes.