While field-programmable gate arrays are used for their flexibility and fast time-to-market, they remain much less area efficient — by about an order of magnitude — than traditional ASICs. That's one reason why developers sometimes have no choice but to use a traditional ASIC.

As semiconductor manufacturing continues to shrink die areas, performance and power consumption of FPGAs will be dominated not by transistors, Flynn said, but by the interconnect between them.

"Is there a way to optimize FPL field-programmable logic power usage by minimizing interconnect power consumption?" asked Flynn. "For FPL to become pervasive this is a problem that has to be attacked."

Flynn said he saw major opportunities for field-programmable logic in the decade ahead. "As interconnect limits cycle time power becomes an important issue. Area, at least in terms of circuit density, becomes a non-issue," he said. "And a system-level rather than processor emphasis favors field-programmable logic."

Flynn sees other compelling themes for the decade ahead, although they could link into a mutually supporting set of converging disciplines.

"Wireless is very important system theme," not only for remote communications but as a solution to interconnect limited structures, Flynn said. "And FPL can be good for multiformat radio, but it can be power consumptive. It does require very efficient channel management.

"Design for reliability, testability, serviceability, recoverability for fail-safe computation — there's a role for FPL in that," he said.

Conventions questioned

Flynn questioned the conventional wisdom that it is inefficient to implement software-programmable processors on a hardware-programmable fabric. Papers on "soft" machines had appeared in IBM Corp.'s R&D journal back in 1984, he said.

"Back then there was a problem with area requirements and they needed an extra cycle for decoders, but they had excellent memory performance. So if we are memory performance limited perhaps we should look at the design of special emulation processors coupled to reconfigurable logic," he said.

Flynn said that his notion of an emulation processor, which would be loaded in and out of an FPGA, was very different and much smaller than the general-purpose processors that run current systems, but would be highly tuned to individual tasks. Pursuing this theme, Flynn said that partial product arrays (PPAs) could support adaptive arithmetic calculations according to required word widths. "Partial product arrays with generalized counters and optimized interconnects could be used of cellular adaptive arithmetic," he said. Small PPAs configured into larger PPAs would be important for "series" calculations, which could be more efficient in area and power than full multipliers, he said.

"Field-programmable logic has the opportunity to be decisive for achieving a new systems-level applications in wireless, computer integrity and image processing," Flynn concluded.