While little is known about the 3GIO spec, a bus charged with supplanting PCI technology in the desktop market, AMD hopes to make HyperTransport an open standard soon, inviting participation in the spec's ongoing development. A HyperTransport industry consortium is imminent, said AMD technology evangelist Gabriele Sartori.

"We have a large number of people working on the spec, and we intend to spread HyperTransport as much as we can throughout the industry," Sartori said.

AMD has working silicon of the technology, and in-house PCI boards on which two chips communicate using HyperTransport. API Networks Inc., which co-developed the spec, last month released a HyperTransport-to-PCI bridge; Nvidia Corp. has a working south bridge; Altera Corp. has shipped FPGAs that support the technology; and multiple MIPS CPUs that use HyperTransport interconnect are in development for the communications market.

Sartori also said a defense contractor, whose name he withheld, contacted AMD in April about licensing HyperTransport. It was the first defense company to do so, he said.

"The set of companies doing real work on HyperTransport is growing so quickly that we need a consortium; it's absolutely needed," said David Rich, general manager of the HyperTransport business at spec co-developer API Networks (Concord, Mass.). "We call AMD almost every week and ask 'Is it here yet?' "

The lack of a consortium has hurt HyperTransport's adoption on the global level, Rich said. "In Europe, especially, companies are very wary until they see a standards body or an open way to discuss things."

Sartori would not disclose who the steering members of the consortium will be but named Broadcom, Cisco, Nvidia and Sun as having helped tweak the spec to broaden its appeal and make it more focused on networking applications. More than 150 companies have licensed the technology from AMD to date, at a minimal fee, he said. "We're not trying to make a business out of this licensing. And we haven't denied a single license to anyone."

"AMD is not restricting the technology at all; the licensing fees are minimal," confirmed Linley Gwennap, president of The Linley Group market research firm (Mountain View, Calif.). "The next best thing to free is cheap. AMD's emphasis now is on getting the technology out there, and at some point a consortium will control the technology's future."

Lawyers and trade show events are all ramping up behind the scenes in preparation for the consortium's unveiling, which AMD said will happen before the end of the year, perhaps before the fall IDF. "We are very serious about making this a success," Sartori said. "The first 70 to 80 percent of the licensees came to us without any public event, and many of those guys would jump into this consortium right away."

Although networking companies constitute about 60 percent of HyperTransport's licensees, the architecture was designed as a PC technology. An "inside-the-box" interconnect scheme, HyperTransport is a serial-link architecture with modular widths of 4, 8, 16 and 32 bits. The low-voltage differential-signaling interconnect features in-band control signaling and was designed to scale below 0.13-micron technology.

Longer legs

While HyperTransport can scale up to 12.8 Gbytes/second today, proponents of the spec say that HyperTransport is more a protocol than a physical interface, so that number can increase easily when necessary. "One of the first things we did when we designed HyperTransport was to map the physical interface for the next 10 years, to show how it scales out for the next 10 years," Sartori said. "So far, we've chosen an interface that was right for the time, but we can go much faster, when we need more bandwidth in the future. HyperTransport has longer legs than people think."

But Intel maintains that HyperTransport is merely a stopgap measure, unable to scale out for the next decade. "HyperTransport is a reasonable solution, but really, it points to the need for a solution," said Bob Gregory, a strategic-planning director for Intel (Santa Clara, Calif.). "We're looking far beyond this. The early days of video took a big step forward with PCI. Those kinds of big steps are done once in a while, and it's a big investment for the industry, so we want to make sure that it scales out two to three process generations."

Meanwhile, proponents of rival networking interconnect technology RapidIO, designed by Motorola and Mercury Computers, say that since HyperTransport was designed as a PC-centric technology, it's wanting in embedded features.

Like HyperTransport, RapidIO is an architecture designed to squeeze more life out of the aging PCI bus. But RapidIO was designed specifically for networking and embedded applications. IBM Corp. this past week joined the RapidIO Trade Association as a steering member and said it will aid in the spec's technical evolution while fitting all of its next-generation PowerPC devices with the RapidIO interconnect.

"One of the compelling reasons for IBM to go with RapidIO was that it was designed with an embedded-systems mentality," said Kalpesh Gala, IBM's PowerPC strategic marketing manager. "If you look at the licensees of HyperTransport, only two or three of them are in the embedded space; the rest of them are server-oriented. It's very hard for me to envision how the embedded space is going to capitalize on HyperTransport."

RapidIO's status as an open standard gives it an advantage over HyperTransport, said Tom Cox, one of the co-chairman of the RapidIO Trade Association and director of strategic planning for Tundra Semiconductor Corp. (Ottawa). "HyperTransport technology tends to be a lot like RapidIO, but it doesn't have peer-to-peer communications. I think the HyperTransport folks are working on that. But then, how would I know? It hasn't exactly been an open forum. It's proprietary."

Concerns addressed

API's Rich said quality-of-service features are being built into the spec, but he wouldn't elaborate. "A lot of server vendors are considering HyperTransport, so we have to look at what kind of features are needed for high-end, enterprise-class servers," Rich said. "At the same time, there are discussions around having networks of HyperTransport devices, so quality-of-service concerns are being addressed there."

Rich asserted that "a lot of the networking and embedded-systems guys are just the kind of companies to prove out the technology before it goes to super-high-volume, desktop products."

Both API Networks and AMD have said they've been approached by a few early Infiniband server startups that are using HyperTransport to connect an Infiniband port on one side with SCSI or Fibre Channel on the other. That interest has come in the form of networking companies' evaluating a MIPS processor, an architecture that has seen HyperTransport adoption via PMC-Sierra, Broadcom and Sandcraft.

Such activity by Infiniband-related companies deals somewhat of a blow to Intel, which has controlled the evolution of the Infiniband infrastructure since the spec was released last fall. "I think it's extremely ironic," Rich said.

"We were amazed by all the people who were talking about Infiniband but had no place to hook Infiniband up," Sartori said. "There are areas where PCI cannot go, so people are building bridges between HyperTransport and Infiniband."

Rich said it's possible that 3GIO will resemble the Infiniband protocol or even be a streamlined subset of it. Every Infiniband startup asked about 3GIO for this article said it was under a nondisclosure agreement that precluded its discussing the spec.

Whereas HyperTransport extends PCI technology, 3GIO will replace PCI and thus will require extensive platform rethinking.

Guaranteed compatibility

AMD claims not to be bothered by the prospect of a post-PCI revolutionary bus architecture. "Intel came so late to this game that I don't really care," Sartori said. "We have no intention to change what we're doing. We have silicon; we have people running Windows over it. Who cares what other people are doing?"

Part of HyperTransport's charm is its ability to remain transparent to the PCI bus, virtually guaranteeing compatibility with PCI-based products and preserving the huge OEM investment in that aging technology. "HyperTransport is done in such a way that it's been able to package PCI commands over a HyperTransport link so that drivers written to interface with devices over PCI can operate without modification," said Nathan Brookwood, president of market research firm Insight 64 (Saratoga, Calif.). "It makes the transition to a new standard a lot easier. It takes out all of the software issues because you've provided compatibility between the two environments."

Bert McComas of InQuest market research (Higley, Ariz.) likened Intel's 3GIO approach to its backing of Rambus technology over double-data-rate (DDR) DRAM. In both cases, McComas claimed, Intel has sought to run interference against a competing, cost-effective spec to promote its own approach.

"3GIO was a reaction," McComas said. "The industry was really dominantly moving toward HyperTransport, and Intel had to do something to run interference. But AMD's in the lead with this one.

"Intel sees HyperTransport run out of the gate, and every horse out of the gate is going in that direction. So Intel wants to jump into the lead and throw itself against the traffic. Intel did the same thing with Rambus, throwing itself in front of DDR and saying, 'If you're big enough, c'mon and take me'."

Intel's Gregory discounted that scenario, saying, "We have no interest in a bus war."

But McComas argued that, "in a sense, every CPU war is a bus war."