At least one major PC OEM, Compaq Computer Corp., confirmed its involvement in the Intel spec's development — and a hunger for I/O harmony.

"Intel has formed a group in the industry to help get the spec defined, and Compaq is part of that group," said Scott King, manager of the platform-engineering group for the Houston-based computer maker's home and office access division. King called the spec, initially dubbed 3GIO, "definitely revolutionary, not evolutionary," underscoring that system OEMs may have to redesign their boxes from the ground up.

"Certainly we'd prefer one I/O architecture," said King, "so that the whole industry wouldn't have to support two infrastructures."

Charles Shaver, a senior member of Compaq's technical staff, said that since Compaq supports both Intel and AMD platforms, "as far as talking between chips, we can live with two different kinds of I/O. The one place I don't want to see a split is where it comes to expansion add-in cards," said Shaver. "We'd really like just one type of expansion slot interface."

According to some industry veterans, getting Intel and AMD to work together on a unified spec is like trying to broker a peace accord in the Middle East. "I certainly don't expect to see what Intel's doing and what AMD's doing come together," laughed Carl Stork, general manager of Microsoft Corp.'s Windows Division. "I think they'll both have the volume support, the critical mass, on both sides."

Others, though, believe the industry can avoid another bus war like the one that pitted NGIO against Future I/O. Camps backing those proposals eventually merged and settled on the Infiniband spec for servers.

"When people try to solve the same problem with similar constraints, they end up with similar solutions," said Nathan Brookwood, president of market research firm Insight64 (Saratoga, Calif.). "The question becomes, 'How can we marry those so everyone can claim ownership?' I hope Intel and AMD can work together on this, but I tend to be an optimist. There are issues that go way beyond technology that would need to be resolved."

Silent bomb

At the recent Intel Developer Forum (IDF), Louis Burns, general manager of Intel's Desktop Platforms Group, detonated a silent bomb when he announced that Intel was working on its third-generation I/O spec, a replacement for PCI. The spec, which looks to prepare I/O technology for the coming age of 10-GHz processors, will move away from shared buses, as in the Infiniband initiative for servers.

"Third-generation I/O architecture has to be full serial; it has to be a point-to-point connection to support the hyperspeeds we're going to be driving this at," Burns said at the time. "We want to have the absolute smallest number of pins with the absolute maximum bandwidth." Also, he said, the bus "has to be scalable to greater than 10 GHz, and it has to be flexible to really adopt the needs of the end user, the OEM and the industry at large."

While the knowledge that shared buses are running out of gas is nothing new, Intel's proposition is. It looks to fundamentally alter the future of desktop I/O technology, forcing OEMs to redesign their systems. And the timetable is aggressive; Burns said the preliminary spec would be ready by the fall IDF.

Burns said that Intel had explored alternatives, such as the AMD-developed HyperTransport, and found them wanting. "We looked inside our own Hub Link architecture and we've looked at a number of other architectures, including HyperTransport, to try to understand whether they had the scalability, the flexibility, the true performance characteristics to become an industry-standard I/O architecture for the next 10 years. The answer is flat-out no," Burns said. "If it's going to last for 10 years, it really will push into the theoretical limits of copper."

Initially calling the next-generation I/O initiative a preliminary spec, Burns, interestingly, also referred to it as a "standard." "This is not a standard we have already in a document. This is a standard that we're going to work very closely with the industry at large to develop," he said.

'Out of nowhere'

While acknowledging the need to replace PCI, just as PCI supplanted ISA, industry watchers were caught off guard by Burns' announcement. "This really did come out of nowhere. If they had been working on it for a long while, it wouldn't be like them to not share the answer," said analyst Brookwood.

But Brookwood expressed concern over the spec and believes the industry would be better-served without fragmentation. "I think AMD's HyperTransport comes closer than anything else out there, and Intel's Burns certainly didn't want to acknowledge that," Brookwood said. "I'm hoping that as they look more closely at HyperTransport, they may discover there's more there than was first thought."

Proponents of HyperTransport, such as API NetWorks Inc. (Concord, Mass.), claim that there's a difference between the physical standard defined by the spec and the overall protocol. "We think that Intel's been surprised and taken unawares that HyperTransport has got the support that it has," said David Rich, a general manager at API NetWorks, which co-developed the architecture with AMD. Rich pointed to a number of wins for HyperTransport, such as its adoption by the MIPS architecture for networking applications (via PMC-Sierra) and similar commitments from Broadcom's Sibyte unit, Nvidia and SandCraft. And major OEMs, including Compaq on the PC end and Cisco Systems in networking, are doing preliminary work with the spec, Rich said.

"We've asked some of the large system vendors, 'are you thinking of going Intel's way?' And they've said they haven't heard anything more about Intel's spec," he said.

"In the IDF speech, they tried to pigeonhole HyperTransport as a simple physical interface: How many gigabits per second can you get over wire? But that's not all that HyperTransport is," said Rich. "It defines a physical standard but also defines a whole protocol that defines compatibility with PCI."

API NetWorks will release the AP1011, a HyperTransport-to-PCI bridge chip that connects the HyperTransport Bus on microprocessors, network processors and ASICs to a variety of PCI devices and peripherals. The first of its kind, the chip is sampling now and will sell for $95 each in quantities of 1,000 when volume production begins in June.

To accelerate the technology's adoption, the company will also license intellectual property in the form of the HyperTransport physical interface and protocols for the design of custom chips and ASICs.

"Our goals were to improve system performance, I/O bandwidth and scalability and to create one link that would be made available to anybody who wants to adopt it, thereby making it an industry standard," Rich said. "It was meant to complement existing buses; it doesn't attempt to replace Ethernet, Fibre Channel or SCSI. It has little or no impact on the OS and the drivers by maintaining a PCI software model."

HyperTransport is a high-speed bus that can move data from processors to peripherals at speeds up to 60 times faster than a 32-bit PCI bus operating at 66 MHz. API NetWorks and AMD set out to develop the spec in order to speed PCI while preserving the investments OEMs have made in PCI technology.

But can the royalty-free HyperTransport scale far out into the future, to the theoretical limits of copper?

"As currently constituted, HyperTransport is not the answer," said analyst Brookwood. "But there's a hierarchy there, and physical implementation is quite separate from the protocol implementation. I think there'd be a way to take the higher levels of HyperTransport, which address API and tunneling type issues, and marry those with an advanced signaling technology, and come up with something that solves Intel's problem."

Marriage benefits

Such a marriage would preserve PCI investment for OEMs, he said. "That way, you could still carry on many of the characteristics particular to preserving the large investment of drivers that have been built for PCI."

Intel, however, is not of the same mind. "HyperTransport is a reasonable solution for what its developers are targeting," said Bob Gregory, a strategic-planning director at Intel who is involved in the I/O technology evaluations. But "we want to make sure that third-generation I/O is a full serial technology that will scale the next two to three process generations. What we see, fundamentally, is that with HyperTransport, there'd be some limitation."

Gregory noted that "Intel began shipping its Hub Link point-to-point high-speed technology two years ago." It's a similar technology, charged with squeezing more performance from the PCI bus. "We see it HyperTransport as being implemented to address that for AMD's platform."

Intel's Hub architecture, featured in the 8XX chip sets, claims to deliver twice the I/O bandwidth of previous generations of north-bridge/south-bridge technology, with dedicated data paths to optimize the additional bandwidth.

When PCI was being developed roughly 10 years ago, the capability to produce a switched fabric was there, but the infrastructure was not, said Jim Pappas, director of initiative marketing for Intel, who helps head the Infiniband Trade Association. "It just wouldn't have been economically feasible; it would've failed in the marketplace." Pappas said that Intel is committed to "replacing copper with silicon, at some point. Because of Moore's Law, silicon actually gets cheaper than copper, over time. We're not there yet, but we will be.

"Buses will continue to get better for some markets and applications. Buses will be around for a long time," Pappas went on. "Either the performance needs to increase to where a particular market needs it, or the cost of switches becomes so cheap that there's no reason not to switch to it — there's a penalty for not going with switches. It appears the desktop industry is starting to come to some sort of agreement there as well."

Is "agreement" the operative word? Or will the promised third-generation I/O spec be the first gunshot in a coming bus war? Stay tuned for the fall IDF.