SAN FRANCISCO — The challenge of keeping processors fed with data and maximizing the data rate of network-centric processors and systems were addressed in an International Solid-State Circuits Conference session on serial digital interfaces. The session also showcased efforts by both Intel Corp. and Rambus Inc. to improve serial data specifications.
Presentations at the session varied from an academic paper on an 8-giga-symbol/second transceiver to papers from industry research teams on serial schemes down to 500 Mbit/s per channel.
Intel representative Matthew Haycock discussed research into a digital router-oriented 3.2-GHz, 6.4-Gbit/s per channel signaling scheme implemented in 0.18-micron CMOS.
And Rambus, which provides high-bandwidth chip connection technologies for PCs and game consoles, disclosed improvements in its Direct Rambus and Quad Rambus Signaling Level (QRSL) interfaces.
Haycock discussed a simultaneous bidirectional scheme that operates at 6.4 Gbits/s over short distances of 15 centimeters, but deteriorates more or less linearly to 2.4 Gbits/s over a 122-centimeter distance across three boards and through two connectors.
It was not clear how such performance would be derated against process variations, temperature conditions and phase if it were made commercially available.
Haycock concluded that the scheme showed "signaling rates on a par with today's processors," and is capable of 5 Gbits/s per channel across all phase conditions.
Jared Zerbe, design manager for Rambus (Los Altos, Calif.), highlighted a 25 percent increase in bandwidth of his company's QRSL signaling technology, in the first of two Rambus papers in the session.
When first announced last June, QRSL was predicted to have a transfer rate of 1.6 Gbits/s per channel. But Zerbe's presentation showed the scheme achieving 2 Gbit/s from a 500-MHz clock.
The QRSL system, which uses four signaling levels in a 800-mV voltage swing, is intended for closed single-board systems with one master, up to four slave devices and no connectors, Zerbe said. A typical application might be the games console market, where Rambus previously worked with Toshiba Corp. on devices for Nintendo's N64 system.
Zerbe detailed the design of a 2-Gbit/s-per-pin single-ended 4-PAM (pulse amplitude modulated) interface and showed measured system margins in a test system representing a low-cost consumer environment.
Among the circuit innovations he detailed were driver equalization and "good neighbor" cross-talk cancellation schemes. The good neighbor scheme allows signals from nearest neighbors to be leaked onto the "victim" pin to negate crosstalk and ground bounce. The circuit Zerbe described was built in 0.25-micron CMOS with a Vdd of 2.0V.
The session's second Rambus presentation, by the company's circuit design manager Stefanos Sidiropoulos, explained "how we increased the Rambus interface from 800 Mbit/s per pin to 1.1 Gbit/s per pin. In terms of the Direct Rambus 16-bit-wide data scheme this translates into a 2.2-Gbyte/s interface."
Innovative techniques were used to allow software-controlled centering of the "receive window," Sidiropoulos said.
The signaling interface for main memory uses a digitally locked loop circuit that enables in-system timing calibration with 1.4 degree resolution and uses output drivers with limited positive feedback to increase voltage margin.
Rambus engineers disclosed technical advancements to the signaling interface by demonstrating prototype chips that operate at up to 2.6 Gbytes/s in a standard CSP package.
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