SAN MATEO, Calif. — Xilinx Inc. this week rolled out the latest spin of its Virtex FPGA family, a device the company believes will take FPGAs to a new class of engineers concerned with system-level issues such as signal integrity, timing and new I/O standards.
Calling its Virtex II the "largest silicon and software R&D effort in the history of programmable logic," Xilinx said its aim was to pack in enough features to encompass platform-level design that can't be addressed with custom ASICs.
Among the most important, the company said, is its controlled-impedance technology, which is intended to take a big chunk out of the time it takes to lay out a printed-circuit board. That's no trivial task, and has been known to take up to eight weeks in some extreme cases.
FPGA boards require at least one resistor per I/O. If you multiply the number of I/Os by 1,000 for every pin on a high-end FPGA, times the number of ICs, the problem becomes clear. "We found out that Cisco has more engineers on pc-board layout than on the FPGAs," said Bruce Weyer, senior director of marketing for Xilinx (San Jose, Calif.).
I/Os Xcite
The Xilinx Controlled Impedance Technology (Xcite), employed on all single-sided I/Os, seeks to solve this by assigning two reference resistors to eight I/O banks with feedback control. This scheme matches the output and the external reference impedance. The feedback control loop also compensates for voltage or temperature swings that can put a damper on performance, Weyer said.
"With the reference resistors, we can adjust the internal impedance to match that of the board, so we can take 1,000 resistors and drop it down to 16," he said. "By doing so we've removed half the traces on the board, which usually requires incredible manpower and complexity."
To address the higher degree of integration per chip, Xilinx bumped up the number of global clock buffer-multiplexers from four to 16, enabling as many low-skew clock domains for each device. Particular attention was given to DLL-like digital clock managers, which were designed for more precise zero-delay clock buffering, clock edge placement and frequency generation.
Xilinx claims the precision of the digital clock managers goes well beyond traditional phase-locked loops or delay-lock loops. It's possible, for example, to place the clock edge within 256 phases to come within 1 percent accuracy. And the frequency generator can have a numerator range from 1 to 4,096, making it possible to take a 1-MHz clock up to 200 MHz, Weyer said.
The clocking features enable Virtex II to support a range of system I/O. For example, the digital clock manager can generate the 50/50 duty outputs for double-data-rate DRAMs. Virtex II also supports ZBT SRAM, QDR SRAM and content-addressable memories. But Xilinx chose not to support Rambus DRAM because of the licensing burden, Weyer said.
Accommodating different I/O standards, memory or otherwise, is being touted as a key feature of Virtex II. Each user I/O pin can support more than 20 interface electrical standards, including PCI-X at 133 MHz, RapidI/O and POS PHY Level 4.
Designers can also build in internal memory by way of the configurable-logic blocks, which have both memory elements and routing resources. Eight 16-bit memory units in each logic block can be fashioned into a 16-bit RAM, a 16-bit variable-tap shift register or a four-input lookup table. Additional logic can connect the logic blocks to create 128-bit RAM, a 128-bit shift register and 32-input/one-output multiplexers. The architecture can also incorporate 18 kbits of block RAM, a hard macro that is designed on a new routing structure which decouples the routing delay from the signal fan-out.
The internal interconnect is geared toward wide data widths for systems with multiple clock domains and independent blocks of intellectual property (IP). The data buses, for example, can drive several ULVDS interface standards to transfer data across a backplane, for point-to-point communications or multicast bus standards, Xilinx said.
The Virtex II is not pin-compatible with previous-generation Virtex-E devices, largely because of the new I/O features. Designers will be able to recompile Virtex-E HDL source code to Virtex II and update their IP cores for the device.
Virtex II will be phased in between now and midyear, and Xilinx expects the family to be in full production by the third quarter. Prices will depend on device density, from 40,000 to 10 million gates, and will range from less than $10 to $1,200.
