LONDON — ASM International NV (Bilthoven, Netherlands) and Philips Research Laboratories (Eindhoven, Netherlands) have produced what they call the world's thinnest transistor gate insulation layer with a commercially acceptable leakage current. The gate was built using a structure that could be applied to semiconductor process technologies featuring 70-nanometer gate widths, the companies said.
Rather than building the gate in silicon dioxide, the insulator used in current CMOS process technologies but expected to pose reliability problems at the 70-nanometer node, ASM and Philips used a layer-by-layer assembly of atoms of zirconium, aluminum and oxygen to produce a stack with a thickness comparable to only four to five atoms of silicon oxide. This arrangement of a few atomic layers produces a material with insulating qualities almost one million times better than silicon dioxide, the companies said.
With an effective thickness of 1.1 nanometers, the layer was deposited using atomic layer chemical vapor deposition, a technique developed by Microchemistry Ltd. (Espoo, Finland), which is now a wholly-owned subsidiary of ASM International named ASM Microchemistry Ltd.
"Our Pulsar atomic layer CVD system with its ability to control both composition and thickness on an atomic level proved to be critical to achieve this exciting result", said Ivo Raaijmakers, chief technology officer of front-end operations at ASM International.
Mart Graef, department head of the semiconductor process modules group at Philips Research Laboratories, said, "This is a key process step in advanced silicon technology. It will enable the manufacturing of devices with a much higher performance than the ones currently in production."
