The report is based on contributions from 113 engineers who attended DAC, spiced with commentary from Cooley. Contributions included commentary on almost every conceivable aspect of chip design, and references to most of the 200-plus EDA vendors, including small startups, who exhibited at the 37th DAC, held last month in Los Angeles.

While hardly a scientific sample, the report suggests some interesting trends. One is that engineers appear very skeptical about C/C++ based design tools but seem keenly interested in Co-Design Automation's proprietary Superlog language. Another is that Cadence Design Systems appears to be regaining some lost ground in simulation, impressing designers with the speed of its NC Verilog simulator and the Affirma Verification Cockpit.

The report found that a plethora of verification startups are stirring up interest, but garnering mixed reviews as well as resistance to what some view as overblown claims. Some reviewers saw synthesis startup Get2Chip as a potentially viable competitor to Synopsys, and others expressed keen interest, mixed with some skepticism, about Magma Design Automation's physical design tools.

The report provided glimpses of some unannounced products reportedly shown in demo suites, particularly from Synopsys. Engineers who attended that company's presentations wrote about Verification Analyst, an assertion-based "white box" verification tool; Ketchum, a semi-formal automatic test generator for verification; and Route66, a cell-level router based on technology acquired when Synopsys purchased Gambit.

Mentor Graphics is reportedly planning to launch a "platform-based" design tool that will serve as a front end to its Seamless hardware/software co-verification suite. Representatives of EDA startup AmmoCore Technology, which was not among the exhibitors,were spotted talking to engineers in hallways about the company's partitioning software for large hierarchical chip designs.

Where's the silicon?

The report opens with a familiar Cooley beef — that many EDA vendors are making bold claims without being able to name customers who have actually taped out chips using their tools. "I insist on at least one very painfully detailed technical customer tape-out story before I even remotely start taking any new tool or methodology seriously," Cooley wrote.

That's particularly true among the new crop of C/C++ design tools, he wrote. "Nobody's used any of this C/C++ stuff to successfully make even one chip."

In comment after comment, engineers contributing to the DAC report derided C/C++ hardware design tools. "They're solutions looking for a problem," said one. Even those who expressed some interest pointed to unresolved problems. The CynApps C simulator may not provide the same answers as the company's synthesized Verilog code, and the Synopsys-backed SystemC class library has concurrency problems, according to one engineer.

Some interest was expressed in C language tools from C Level Design, Frontier Design Automation and CoWare. But by far the strongest contender for a next-generation design language, if this report is a representative sample, is in the Superlog language from Co-Design Automation.

"A number of doubting designers are giving Superlog a decent second look because it's not a replacement for Verilog, but a superset of Verilog," said Cooley. A number of engineers who submitted reviews thought likewise. "Superlog takes what HDLs do best and enhances the capabilities, instead of trying to replace the HDL with C," wrote one.

Elsewhere in the high-level design area, Cooley noted that electronic system design automation (ESDA), a key DAC theme several years ago, has all but disappeared. For this topic, the report yielded only a couple of postings about startup TransModeling.

In the functional verification arena, several new capabilities garnered favorable reviews. One was Ikos Systems' transaction-level interface, and another was Axis Systems' "VCD on demand" capability. But amidst several favorable reviews about Axis was a charge that the company made the "biggest lie" at DAC about compilation speeds.

Surprising this year, according to Cooley, were several favorable reviews about Cadence's Affirma Verification Cockpit, which bundles such capabilities as testbench generation and linting with simulation. A couple of postings cited Cadence's NC Verilog as the fastest Verilog simulator, surpassing Synopsys' VCS. Others, however, liked the VeriC/DKI C language interface that Synopsys is reportedly building into VCS.

Testbench generation was a hot topic, with some engineers wondering if C/C++ tools will kill off proprietary testbench languages. Several postings expressed contempt about the increasingly bitter marketing war between Verisity and Synopsys' Vera product group, in which each is now claiming to have majority market share.

One of the most notable features of this year's DAC was the high number of verification startups, and most were mentioned in the trip report. 0-In Design Automation, Averant, and Innologic were among those who got good reviews. But startups Real Intent and Levetate drew criticism for what some saw as marketing hype and misrepresentation of products.

In the lint area, TransEDA was by far the most mentioned company, although its new book on verification methodology was criticized as self-serving. In formal equivalency checking, a market shift may be under way. Several postings praised startup Verplex's LEC tool, along with Mentor Graphics' new FormalPro, as offering better performance and functionality than the market leaders — Avanti's Design Verifyer and Synopsys' Formality.

Synopsys may face some synthesis competition from Get2Chip, if the DAC reviews are any indication. "Get2Chip looked really hot," wrote one engineer. "Not only are they bucking for RTL status, they also have a firm grasp on what they call architectural synthesis."

Magma made a big splash at this year's DAC and was criticized by Cooley for a lack of "credible" tapeout stories. But the company attracted a high level of user interest. "I'm very, very convinced about the success of Magma," wrote one engineer. But others cited the company's lack of a track record.

Magma's rival startup, Monterey Design Systems, drew fewer responses. The company was criticized for slow progress and lack of an ECO capability. But there were positive reviews, too. "Instead of overmarketing vaporware like Magma, they actually have thought about the tool and have been quietly refining it. They look good," said one engineer.

Synopsys' Physical Compiler, dubbed "PhysOpt" by most respondents, appears to have more actual users than Magma or Monterey tools. But several reviewers said the product needs a detailed router. The upcoming Nano physical design system from Cadence, dubbed Integration Ensemble by one engineer, attracted some interest but also concern about a relatively closed database.

Cooley identified two "technology finds" that particularly impressed him. One was GeneSys Testware's BISTDR memory built-in self-test product; another was Prosper Design's HybridMaster design planning tool. As always, the report concluded with an overview of the best and worst parties and giveaways.