Following the lead of IBM Corp., which has long been banging the drum for SOI, Motorola Inc., Advanced Micro Devices Inc. and Texas Instruments Inc. are jumping on the SOI bandwagon, drawn by potential performance gains of as much as 20 percent. Also, IBM reportedly will serve as the foundry for a Hewlett-Packard Co. RISC processor built in SOI, and TI will apparently do the same for a Sun Microsystems Sparc CPU.

"Good for them," said Mark Bohr, director of process architecture and integration at Intel's Hillsboro, Ore., facility, when presented with the growing list of companies adopting SOI for their high-end processors. "I don't want to change their minds," he said, adding that SOI may prove "very painful" for Intel's competitors.

But Bijan Davari, IBM's vice president of logic technology, likened SOI to a "wild horse that, once you tame it, can give you a lot of power. People at Intel haven't been able to figure it out yet."

IBM's Microelectronics Division has been trumpeting the performance gains possible with SOI for several years. Besides moving nearly all of its own performance-hungry processors to SOI, IBM will serve as the foundry for an HP-PA RISC processor design in SOI technology, according to reliable sources.

At the VLSI Technology Symposium here this past week, managers from Motorola's Semiconductor Products Sector told EE Times that the company will use an SOI process — initially at 0.18-micron design rules but moving quickly to 0.13 micron — to build an Altivec G4 PowerPC processor.

The chip is to sample late this year and go into volume production in mid-2001. Performance will be "well over a gigahertz," said Suresh Venkatesan, who is in charge of developing Motorola's 130-nanometer (0.13-micron) technology.

Following that, Motorola will make DSPs, network processors, cellular basestation chip sets and other performance-hungry ICs with SOI technology starting in 2002, said Fabio Pintchovski, director of technology for Motorola's networking and computing systems group.

Several sources said AMD, which co-develops its logic process technology with Motorola, will use an SOI process for its K-8 microprocessor, code-named Sledgehammer. Nick Kepler, director of logic technology development at the AMD (Sunnyvale, Calif.), declined to comment on product plans, but cautioned that "SOI wafer availability is the biggest issue" facing companies with significant volumes.

For its part, Texas Instruments is developing an SOI process that will serve as a high-performance module in TI's 130-nm process generation, said Yoshio Nishi, director of silicon R&D at TI (Dallas). "The fact is, at 0.13 and 0.10 [micron] design rules, SOI has definite advantages over bulk [silicon]," Nishi said. If SOI can deliver a 20 percent performance gain, that would equal the speed boost derived from moving to a new process generation, he noted.

Though Nishi would not comment on product plans, reliable sources said a team at Sun Microsystems is designing a Sparc processor that will be manufactured on TI's SOI process, with volume shipments expected in mid-2002. However, Pankaj Dixit, director of microelectronics technology at Sun (Mountain View, Calif.), declined to confirm that report, saying only that Sun is currently evaluating SOI.

Advantage at 0.18 micron

Intel now acknowledges that at the 0.18-micron generation, SOI circuits run faster than bulk CMOS devices, largely because SOI effectively eliminates junction capacitance. However, as CMOS scales to 130 nm, 100 nm and beyond, SOI's performance edge will diminish, the company maintains, largely because junction capacitance will decline relative to total parasitic capacitance. Capacitance at the gate and in the interconnects will dominate at the 100-nm technology node and beyond, Intel holds.

SOI insulates transistors by building them on a silicon film atop a buried layer of oxide across an entire wafer. Until recently it has been considered an attractive but difficult technology. Implanting a layer of oxide takes several hours on an expensive implantation machine, while bonding a silicon wafer with an insulating substrate also is expensive. SOI wafers suffer from relatively frequent stress-induced defects in the silicon, and from pinholes that occur in the buried oxide.

Beyond the physical infrastructure, SOI is equally challenging to circuit designers. Drawing the performance gains from SOI requires new EDA tools, SOI-specific circuit models and retraining design teams.

Even as more companies gravitate toward SOI, others, including Intel, argue that simply scaling bulk CMOS brings an equal payback for the effort expended. And for high-volume, cost-sensitive products, the added wafer costs of SOI are significant, this camp holds.

However, Ghavam Shahidi, senior manager of IBM's SOI program, said he expects the cost of SOI wafers to decline substantially, predicting a "$100 adder" at the 0.13-micron generation. He called that insignificant for wafers holding value-added products, such as microprocessors.

Meanwhile, Intel is moving to 300-mm (12-inch) wafers starting next year. By contrast, SOI wafers at the 200-mm diameter size are only now reaching volumes, in quantities far too modest for Intel's voracious appetite.

Moot point

Indeed, "wafer availability alone makes SOI a moot point" for Intel, Bohr said. And since high yields are essential to a healthy bottom line, Bohr emphasized that SOI yields compare poorly with those possible with bulk-silicon wafers.

Moreover, switching to SOI would require new EDA tooling, circuit models and training in "a tough design methodology," he said. Despite those difficulties, Intel would surely make the switch if convinced of the performance gains, said Intel senior engineer Kaizad Mistry. However, in what surely will be a much-debated paper, Mistry argued at the VLSI Technology Symposium that whatever speed advantages SOI technology may have at the 0.18-micron generation will diminish over time.

Intel created 0.18-micron SOI circuits, the "best reported to date" for 0.18-micron design rules, he said. Mistry's team in Portland, Ore., built test circuits using Intel's bulk 0.18-micron CMOS process and compared them to circuits adapted to SOI wafers. Mistry reported a 16 percent performance gain for SOI for an inverter with a fanout of 1, an 8 percent gain for an inverter with a more typical fanout of 4 and a 20 percent improvement for a three-input NAND.

That 15 percent gain was countered somewhat by the need to create a "guardband" for the so-called "history effect," reducing the net gain to only 10 percent, Mistry said. SOI transistors typically switch more slowly after an initial "on" state because the body is "floating" — that is, not connected to a grounded substrate. Since it is impossible to predict which transistors are suffering from the history effect, the circuit designer must create a guardband of 5 to 7 percent to ensure a predictable transistor performance on an MPU with millions of transistors, said Mistry.

The performance gain at 0.18-micron design rules might have tempted Intel, except that the wafer and design infrastructure was woefully lacking. The Intel team forecast that at the 0.13-micron generation, the performance gains stemming from the lack of junction capacitance in an SOI technology would diminish.

Intel believes that it is well ahead of other silicon vendors in terms of reducing junction capacitance in its bulk CMOS process. As scaling proceeds, and junction capacitance plays a smaller role vis--vis gate capacitance, the SOI advantage in terms of parasitics in the junction regions will fade to insignificance, the company contends.

Bottom line, by Mistry's accounting: By the 100-nm generation, SOI's advantage is only 3 percent. And that ignores the interconnect load, which erodes the SOI gain even further, Mistry said. For all of those reasons, SOI has no appeal to Intel, he concluded.

Floating bodies

Everyone agrees that SOI circuit designers must deal with the floating-body effect. Where the argument starts is whether the floating body and the resultant history effect are a detriment to performance, as Intel argues, or can be turned to an advantage, as IBM's Davari contends.

An SOI device is insulated on all directions by oxide, on the right and left by shallow trench isolation and on the bottom by the buried-oxide layer in the SOI wafer. The active area of the transistor is a very small silicon volume that is said to "float" because it is not directly connected to anything.

Lacking an ohmic contact to ground, the potential floats between the top layer and the buried oxide. And with limited connections through source and drain, but no direct contact, the body voltage can change, giving rise to the floating-body effect, as well as a number of other issues, such as changes in the breakdown voltage.

Since the voltage changes as the gate is turned on, the threshold voltage actually drops when the transistor is turned on, resulting in higher current. "The key thing is, how do you control it?" said Davari. "At other times, when the device is off, you don't know exactly what the voltage is. But there are ways of knowing what it is so that you can harness the performance gain as it is switching."

Venkatesan said that at Motorola, the push for SOI came from the design engineers themselves, not from the process technology development group. "The floating-body effect allows a more flexible design effort," he said.

By learning about SOI's inherent quirks in high-performance designs, Motorola expects to extend the technology to a broad array of products over the next several years.

"An important part of getting good performance from SOI is the development of good models so that you get the full advantage of the floating-body effect," concurred Bob Yeargain, director of CMOS device development at Motorola.

Motorola, like IBM and other companies, will maintain parallel processes in bulk and SOI technologies for the 130-nm generation. Indeed, IBM's Davari said ICs made in bulk CMOS will outnumber SOI-based products by a considerable margin over the next five to 10 years.

"Much of the communications area will remain in bulk, and bulk will be used wherever it provides adequate performance and power," he said. "What we are saying is that the ratio will increase toward SOI in the industry.

"We believe as you go to 100-nm technology and beyond, it will be very difficult to get device scaling in bulk. To achieve performance gains, we believe the industry will need SOI, and we believe we can go to shorter-channel-length devices with SOI. A lot of very interesting, novel structures can be built with SOI that you can't do in bulk."