Developments in device engineering from companies and research laboratories presented here at the 2000 Symposium on VLSI Technology suggest the industry is on track to the 0.10-micron technology node. According to Intel Corp., they will probably reach that level in the next 2.5 years.

Among the most promising signs: evidence that 70-nm gate-length CMOS devices are around the corner; promising work on 50-nm transistors; and developments in gate electrode materials and engineering.

"I don't see any fundamental physical barriers at least down to 50-nm [gate length]," said Craig Lage, a manager of technology development for Motorola Inc.'s Semiconductor Products Sector (Austin, Texas).

Despite the progress, researchers here said traditional scaling of CMOS by knocking down both the supply voltage and transistor threshold voltage with every new lithography step will come to an end, largely because of growing standby power concerns.

"The benefit of scaling has always been density, performance and power," said Mark Bohr, director of process architecture and integration for Intel's Portland Technology Development Center (Hillsboro, Ore.). "What I'm afraid of is at 50 to 35 nm, you won't be able to get all three. You'll get two out of three."

Masao Fukuma, general manager of NEC Corp.'s Silicon Systems Research Laboratories, said the industry must find a way to do "equivalent scaling." That will include the use of new materials to keep shrinking the transistors, plus new advances in architecture and circuit designs. "The scaling principle has been driving VLSIs," Fukuma said. "However, at less than 100 nm, the improvements will saturate."

It is urgent, for example, for chip makers to take into account fluctuations in threshold voltage and wiring characteristics in sub-100-nm gate-length transistors on the same chip, he said.

None of this, however, is slowing device engineers' efforts to meet their timetables for reducing the size of transistors. One encouraging sign came from Intel, which said it will use 70-nm gate-length transistors with its upcoming 0.13-micron (drawn) process technology. Intel is planning to disclose details of its process this fall and is expected to bring it onstream next year.

Similarly, NEC presented a paper on a 70-nm gate-length CMOS technology for 1-volt operation, which the company claims meets the device requirements laid out by the International Technology Road Map for Semiconductors. The technology uses low-energy ion implantation to form the source and drain and thin 1.3-nm gate oxides.

Both suggest that chip vendors have — at least at the transistor level — punched through the 100-nm wall, a precursor for devices that will be fabricated at the 0.10-micron technology node and below.

Moreover, devices with 50-nm gate lengths are coming within range. Advanced Micro Devices Inc. said it fabricated a 50-nm CMOS device using a nickel-silicon-based salicide. And Intel was to present a paper suggesting that it can scale conventional planar CMOS transistors below 50 nm using conventional gate dielectric.

The nickel-silicon material used by AMD is one of the candidates to replace cobalt-silicon and titanium-silicon used to cap the gate electrodes — which are getting narrower with every process generation. AMD claims it was able to achieve a low 2 ohms/square of resistance and low junction leakage, thereby improving drive current.

Intel's Bohr said 2 ohms/square of resistance used to be common, but that contact resistance has been growing to as much as 10 ohms/square as the gate gets thinner. The move from titanium-silicon to cobalt-silicon helped reduce that resistance, but cobalt probably will have to be replaced at some point below 100 nm.

Gating factor

One possible solution presented by researchers at the University of California, Berkeley, is using a dual-metal-gate CMOS. Compared with conventional polysilicon, a dual-metal gate does more to reduce resistance and solve other problems like gate depletion and dopant penetration, the authors said.

Bohr said metal gates may indeed become a necessity. "Perhaps we have to go to all-metal gates to get low resistance and get rid of parasitic capacitance," he said.

Progress was reported on gate insulator materials to replace silicon dioxide, which is expected to lose its insulating properties when it scales to 15 angstroms. Researchers are monitoring the use of high-k dielectrics to replace silicon dioxide so that leakage current doesn't get out of hand. Motorola, the University of Texas at Austin, Toshiba Corp., Taiwan-based Chiao Tung University and Yun-Lin Polytechnic Institute presented papers on high-k materials that could do the job.

Though work has been done on developing high-k materials to build smaller DRAM capacitors for some time, observers said those materials may not be suitable for interfacing to a transistor electrode. Right now there are a number of materials being studied for transistors with k values from 4 to 100. "I think one winner will emerge," said Motorola's Lage.

Still, microprocessor vendors are showing signs that they can tolerate high leakage current in order to maximize performance. In its paper, Intel said it could use a conventional nitrided silicon dioxide down to the 50-nm gate length and tolerate gate leakage of 100 A/cm² — or 100 times greater than the conventional wisdom.

During a discussion, Intel researcher Scott Thompson, the paper's co-author, said companies will no longer be able to develop a one-size-fits-all process at each technology node, and that holding back gate-oxide scaling in order to cut back leakage current is "not realistic."

Others see a similar trend. "High-performance MPUs can take high leakage," said Lage.

While that gives chip makers some wiggle room, things still get rough around 50 nm. Intel has fabricated 50-nm transistors, but they are still deficient in some areas and several years away from completion, Bohr said. "Nobody can make a good 50-nm transistor today," he said. "You see lots of papers, but they do not have the performance they need."