Two supporters of SystemC — Frontier Design (Leuven, Belgium) and Synopsys Inc. (Mountain View, Calif.) — will demonstrate tool sets that shorten the time from algorithm development to custom silicon. Frontier's A|RT Designer tools make C, the language for high-level algorithm development, the mouthpiece for a synthesis engine. Synopsys' introduction allows designers to shorten the steps between high-level floating-point math simulations and practical fixed-point implementation.

In fact, PLD manufacturer Xilinx Inc. (San Jose, Calif.) and simulation tool maker The MathWorks Inc. (Natick, Mass.) will announce a partnership that proposes to do much the same: shorten the jump from C-based algorithm simulations to working silicon. The two have agreed to partner in developing a tool set that will map algorithms — especially math-processing routines — into spaces on Xilinx FPGAs.

TI extends Code Composer

Those announcements follow Texas Instruments Inc.'s announcement last week of version 1.2 extensions to its Code Composer Studio development tools, intended to increase the efficiency of designers working in C. The tools, which include enhancements to the DSP/BIOS real-time kernel, allow a visual linking between compilers and their hardware targets.

Enabling what TI calls profile-based compilation, the tools automatically plot a 2-D graph of code size against performance. That lets users graphically select the optimum combination of code size and speed for their applications, said Rich Scales, product manager for compiler technology. Most significantly, it brings the performance of C-compiled programs for TI DSPs to within 80 percent to 90 percent of what can be obtained with hand-coded assembly language programs, according to TI.

"Developers have been pushed by TI to use C. Now they are starting to use it," said Herman Beke, chief executive officer of Frontier. The Open SystemC Initiative, which Frontier spearheaded with help from Synopsys and others, is intended to establish an interoperable, open modeling platform for C-based designs. Users can download the SystemC modeling platform, which includes the SystemC specification, source code and reference manual, from the Open SystemC Web site.

Introduced at the Date Conference in Paris last month, A|RT Designer is an interactive tool that will synthesize VLIW hardware architectures from C-language software descriptions. Most significantly, the tool will synthesize VHDL or Verilog register-transfer-level descriptions directly from C. "C is the language of system design," Beke said.

His A|RT Designer will help developers interactively optimize C-language algorithms for FPGA or system-on-chip (SoC) implementations, said Beke. The hardware architecture can be modified to optimize for performance, silicon area or power consumption. A data-flow analysis technique built into the tools examines the sequential C code to find operations that can be executed in parallel. So DSP algorithms that have depended on clocks of 300 MHz or better can be parallelized to execute efficiently on hardware with clocks as low as 10 MHz.

Frontier and its partners in silicon may wind up competing against TI on this front. Algorithms constructed for general-purpose VLIW processors can be retargeted for slower implementations like FPGAs — saving power consumption in the process.

The Synopsys C tools, meanwhile, tackle the knotty problem of converting floating-point algorithms into fixed- point implementations. Called CoCentric Fixed-Point Designer, the tool set applies an interpolative analysis to the C source code input. It automatically converts floating-point data types to fully executable SystemC fixed-point data types, said Chris Cavigioli, the technical marketing manager at Synopsys. The new product builds on the CoCentric System Studio announced at last month's Date 2000 conference.

Engineers typically develop signal-processing algorithms for telecommunications, multimedia and voice applications using ANSI-C with IEEE floating-point data types. Since they typically use less silicon, fixed-point implementations must meet the power, cost and portability demands of handheld, battery-powered consumer electronic devices, Cavigioli said.

But conversion is typically time-consuming and often error-prone, since ANSI-C has no native fixed-point data types. Engineers must often find solutions through trial and error.

Synopsys has had a number of project successes to report, including a high-order closed-loop controller designed by Voyan Technology. "Given that Fixed-Point Designer presumes no structure to the algorithm, it represents a valuable contribution — especially because of the interpolation step," said Jim Waite, Voyan's real-time engineering manager. "We generally consider the tool to be useful and time saving and it fits well into our Matlab-oriented flow."

Matlab, from The MathWorks, is one of the most popular tools for high-level DSP algorithm development. Until now, though, there were no easy ways to convert the specialized C used for Matlab simulations into VHDL or Verilog to drive a synthesizer for ASICs or FPGAs, or even the code to program a TI or Motorola general-purpose DSP.

The partnership announced here promises to forge a link between The MathWorks' Simulink products and Xilinx's FPGAs. "The biggest obstacle that designers have had to overcome when using FPGAs in DSP applications has been transitioning from a system-level design representation to an FPGA hardware implementation," said Per Holmberg, Xilinx's product marketing manager.

No product is being announced yet, but a mockup will be shown at the DSP World Exhibition. Called the Xilinx Simulink Interface, the product will likely ship in the third quarter, said Holmberg.

Other C-language products, however, are coming sooner. TI's Code Composer Studio 1.2 is available now for C5000 and C6000 DSPs. The complete Code Composer Studio 1.2 for either DSP family platform is priced at $2,995, including the DSP/BIOS II tool, and with no run-time licensing fees. Updates are scheduled to be sent to currently registered users.

DSP/BIOS II supports all TMS320C5000 and 6000 DSPs that are in production, and it will be extended to new products as silicon becomes available. Compile tools for either family can be purchased separately for $1,495, debug tools for $1,995.

Two versions of the A|RT Designer architectural synthesis tool are available now: A|RT Designer and A|RT Designer Pro. A|RT Designer targets designers who need to get a design done quickly and who have some flexibility in the design's constraints. A|RT Designer Pro offers a wider variety of pragmas that allow finer granularity in optimization. Both tools are available for HP-UX, Sun Solaris and Windows NT platforms. Prices for A|RT Designer start at $65,000 per seat.

Synopsys' CoCentric Fixed-Point Designer will be available in June. Pricing is $6,600 for a one-year term license or $20,000 for a perpetual license.