SAN JOSE, Calif.—Ensuring IC quality while meeting time-to-market demands in the SoC era will require mutual understanding and cooperation between the IP, EDA, and manufacturing sectors. That was the message here in back-to-back panels at the IEEE ISQED Conference.
In two separate Wednesday panel sessions, speakers from academia, the design community as well as the EDA, IP, semiconductor and manufacturing fields helped frame how the complexities of the SoC era could threaten IC quality.
Designing and verifying multimillion-gate systems on chip that target new processes and push the limits of physics—all with one eye on time-to-market—will make quality of design a prime concern in the near future. But verification reuse, process-verified IP and platform computing could help.
In the first panel, hosted by Rita Glover of EDA Today and TechOnLine, six panelists tackled the question of how to ensure IC quality in the face of shrinking time to market windows. Panelists included Intel's Tomm Aldridge, Scenix Semiconductor's Bulent Celebi, Altius Solutions' Aurangzeb Khan, Tensilica's Chris Rowen, Mentor's Ian MacKintosh, and Synopsys' George Swan.
While the panelists agreed that quality is of utmost importance, they varied on what degrees of quality assurance will be required to meet TTM demands. MacKintosh, Mentor's director of engineering, said quality design is key for making time to market windows.
"I'd argue that you will have a hard time getting your product to market if you don't ensure the quality of your design," MacIntosh said. "The issue is not having quality only in the area of design, it is having it throughout the process." Quality must be observed across all the disciplines from spec to production, he added.
Tomm Aldridge, director of Intel's Advanced Systems Laboratory, warned that designers will become overloaded and burn out if they are to have process knowledge in addition to system knowledge for SoC design. "These people have a hard enough job as it is," Aldridge said. "What we need are more tools that hide the errors of manufacturing."
In the keeping with his Intel roots, Aldridge proposed three laws, all of which must conform to Intel's stringent Cost, Quality and Schedule (CQS) requirements. Tomm's Laws include (1) make sure quality goals exist first, (2) validate the design flow, and (3) make sure design quality is achieved before you optimize your design.
Structured vs. loose
Bulent Celebi, president and chief executive of Scenix Semiconductor, said a group at National Semiconductor developing microprocessors enforced a highly structured method, a highly structured business plan, met TTM consistently in less than 6-month time frames and had more than 90 percent first silicon success.
He then compared it to his stint at the more profitable Analogy, which used a "loose process," had "after the fact documentation," two- to three-year turn around and "multiple silicon failures."
"Which of these companies is known as having innovative products," said Celebi. He argued that innovation comes from diversity and that "diversity be definition can't be structured." Celebi instead suggested a hybrid methodology.
"A potential solution may be for your company to pick a particular aspect of the design that is going to make the most impact and loosen up on the engineers creating that innovative part of your product," he said. "At the same time, keep the quality constraints on the rest of your design. That way you still get enough innovation but still have the controls."
Aurangzeb Khan, president and chief executive of Altius Solutions Inc., said his company created its original product and customized derivatives using a platform based design methodology. Khan showed examples of two SoC. The original product took 12 to develop and three more months to reach time to volume and required 70 engineers. The derivative product, which added a DSP block to the design and had less memory, took less than three months to develop, two more months to reach TTV and only required 10 engineers.
Both products required about the same amount of verification, but that the company was able to reuse about 600 verification scripts for the second product, Khan added.
Eye on process
In the second panel, hosted by noted Carnegie Mellon Professor Andrzej J. Strojwas, panelists agreed that technology-independent design is indeed dead and that more attention to the link between design manufacturing and processing will be required to ensure design quality.
Panelists included James Spoto of Conexant, Mark Templeton from Artisan Components, TSMC's Pin-Nan Tseng, PDF Solutions' John Kibarian, and Resve Saleh from Simplex Solutions.
The catalyst of the discussion was kicked off when Tseng, director of new technology at TSMC, laid down TSMC's product roadmap which showed several new complex deep submicron processes, from 0.15 down to 0.10-micron, and derivatives going on line over the next couple of years.
The panel concluded that ensuring quality is maintained for companies targeting these complex processes early in their life will require highly customized physical libraries, will require designers and/or the tools they use to understanding more about the back-end physical effects, require the use of OPC technologies, and may—for performance as well as quality's sake—require IP vendors to model their cores to each complex process.
The panel agreed that designers have to get up to speed on issues such as IR drop, clock skew, capacitative coupling and inductive effects. The panel said that many of these process issues will likely be ironed out by the time the processes become attractive to the mainstream ASIC market, but it also warned that managers should become aware of the process-specific problems, ramp up on the latest design to manufacturing tools, and educate their engineers sooner rather than later.
