The 870 chip set will use a cache coherent link called a scalability port which will allow OEMs to attach multiple four-way SMP processors into larger, more powerful systems with distributed system memory. The chip set is targeted at the next generation 32-bit Foster processors expected to ship late this year and the 64-bit McKinley processors which will ship next year.

To date Intel's chip set work has focused on enabling systems using two, four or eight processors. "With the new scalability port we can link two or more 4-way systems," Rattner said. "This allows OEMs to build 8-, 12- or 16-way systems."

The chip set could also be used by server makers such as Data General, Unisys or IBM's Sequent group that make non-uniform memory access systems based on clusters of SMPs tied together. Using the scalability port could help these OEMs deal with increasingly fast processors such as the 1.5-GHz chip demonstrated here yesterday (Feb. 15).

However, Rattner said he expects such system makers to continue to build a tier of specialty higher-end systems, — beyond the reach of the systems built with the 870, — as they attack the high end of Sun Microsystems' server line.

Intel's 870 chip set will support both Direct Rambus and DDR memory, Rattner said. Because it is focused on enabling groups of 4-way SMPs that might use no more than 8 Gbytes of main memory, Rambus is still available option for such designs, he added.

Rattner said Intel will not detail the specs of the scalability port until its Fall developer's conference, but he suggested the port is fully cache coherent and can handle throughput of multiple gigabytes/second.