Brad Benschneider, a senior member of the technical staff at Compaq Computer Corp., said Compaq's ability to push the Alpha processor to gigahertz levels drew upon a 0.18-micron process, new packaging, and circuit-design improvements. "The metal stack was unchanged from the previous implementation," he said. "It simplified development and meant that we could reuse wire-bond pads for wafer probing."

Circuit performance improvements came from the use of low-threshold transistors in critical macros. This was particularly important in source-follower circuits; the team developed a CAD tool to find and modify these circuits. Because low-threshold transistors are more susceptible to noise, they were not used in dynamic circuits.

Low-threshold transistors formed the cornerstone of IBM Corp.'s G6 processor for S/390 mainframes. As with Compaq's Alpha project, IBM developed a tool to identify candidates for low-threshold switching.

Tom McPherson, engineering manager of server development at IBM, said: "Instead of using dynamic logic, we added low V_t [threshold voltage] transistors wherever it was acceptable in critical paths until all the transistors in the path were low V_t devices, if necessary."

Better body control

IBM's second-generation silicon-on-insulator (SOI) PowerPC was developed to try out a range of circuit techniques, the most important of which was the use of body-voltage control to improve switching speeds on critical paths. Running at 660-MHz on a 0.18-micron process with copper interconnects, much of the speed improvement compared with the 550-MHz design unveiled at last year's ISSCC was due to circuit improvements, according to IBM advisory engineer Tim Buchholtz.

"Body control is a viable technology for leveraging SOI to achieve higher performance. A number of parts ran in the gigahertz range," said Buchholtz. Strict time budgets were used to help build a single-issue PowerPC implemented in bulk CMOS, said Peter Hofstee, senior member of the circuit's design team in Austin, Texas.

"We used a design template to implement almost all of the logic; 470 ps was budgeted for logic," said Hofstee. The remainder of the 1,000-ps budget was taken up by wire delays, register read time, signal distribution and clock uncertainty.

Close attention to design budgeting was also used by Motorola for its 780-MHz PowerPC and by the Intel team developing the 0.18-micron Coppermine. "If you are looking for novel circuit techniques in this design, then you will be disappointed," said Peter Green, design manager for Intel. "Our performance improvements came from engineering discipline."

Focusing their attention on the RC delays caused by long on-chip wires, the Intel team used manual placement and routing together with buffer insertion to ensure that critical paths were dominated by transistor, not interconnect delay. This would make the resulting design more amenable to scaling, Green said.

Dynamic clock control has become the key method for debugging the gigahertz-speed microprocessors presented at this year's ISSCC. Intel has used the technique to temporarily fix a timing problem in its forthcoming Itanium processor. The processor uses a novel clock regeneration and de-skewing approach that localizes clock control to small regions of the chip. Stefan Rusu, principal engineer and manager for Intel, said, "We can delay the clock by programming a delay control register. We used this in one region of the chip to save a partial restepping that would otherwise be needed to fix a timing problem. It allowed earlier sampling of the Itanium processor to customers."

The technique works by extending the clock cycle or changing its duty cycle, giving enough time for the problem path to complete its work before the next cycle begins.

Intel developed a second on-chip clock control circuit that was designed to overcome the problems of driving the part's 800-MHz from a chip tester. This on-die clock shrink unit selectively compresses or stretches the global clock and debugs a variety of critical-path timing problems.

Test features

Testers are struggling to keep up with high-frequency microprocessors. The accuracy of the ODCS unit is an order of magnitude better than the clock edge placement of the best available tester, said Rusu. For its 0.18-micron SOI-based PowerPC processor, IBM developed its own form of clock control circuit to tune the speed of the Level 2 cache to that of the processor core itself and compensate for speed problems caused by process variations.

Buchholtz of IBM said that "the Level 2 cache data bus might have resulted in cycle-limiting timing. So we added the programmable delay block macro to handle situations where set-up times would be insufficient.

Hewlett-Packard Co. extended the on-chip logic analyzer support introduced on its earliest PA-RISC processors to remove entire clock cycles and swap between two unrelated external clocks. "This allows very fast debug," said Kevin Hurd, a member of HP's technical staff. "We also made several clock domains programmable to allow silicon tuning."

The G6 processor developed for IBM's latest range of S/390 servers were provided with on-chip clock-control circuits. The design uses two processors running in lock step on the same chip to avoid processing problems caused by soft errors, and needed to be tested under a wide range of conditions during burn-in.

Clock control allows additional stress-test capability, said Tom McPherson, engineering manager of server development at IBM.

Sun Microsystems' new processor introduced asynchronous design techniques for key logic paths to ensure that the design would be able to run at least at 800 MHz. The high-speed paths used a delayed-clocking form of domino logic driven by multiphase clock signals. Using this scheme, critical signals are never controlled by the clock, so they are able to run through the chip at maximum speed. Consecutive logic stages are clocked by delayed phases with enough overlap to guarantee that transitions are safe until the logic meets the next clock phase. Latches are used to catch logic when the processor runs at slower speeds for debug to ensure safe timing.

"We use a latency latch. It kicks in when the clock stretches out to the signal until the clock is ready," said Ray Heald, a distinguished engineer at Sun. "If you're going to go through two cycles, you need to have something there to catch it."

With 11 million logic transistors, for a total of 23 million on the die, the Sun team could not use custom design techniques throughout. Instead, they used an ASIC-style flow for much of the design, using static CMOS logic created by synthesis tools which was then placed and routed automatically. Where synthesized logic was not fast enough, they used a hybrid approach in which dynamic logic cells were placed manually but CAD tools were used to shield wires, insert clocks, power and ground signals. The critical paths were designed using full-custom techniques. Wire shielding formed a crucial part of the design. With crosstalk a major problem at 0.15 micron, wires were analyzed to see if coupling effects would cause problems.

Less accurate

Applied hierarchically to all blocks and to the top-level interconnect after parasitic extraction, the technique was about 20 percent less accurate than full Spice simulation. Thousands of violations caused by crosstalk noise were found and were fixed by changing wire spacing, inserting or resizing buffers, and by shielding vulnerable wires.

Power consumption of 60 W at with a 1.5-V supply voltage could have resulted in severe IR drops at key points on the chip. The flip-chip bonded die has 1,735 power bumps, or more than double the number of I/O pads. A double grid on metal layers five and six provide power. The grid elements in the sixth layer are attached to thick wires in metal seven that act like busbars on a backplane. On top of that, the chip has a total of 220 nF of decoupling capacitance together with a number of on-chip voltage regulators to reduce problems caused by high di/dt rates.

One distinctive feature of the Sparc architecture is its support for register windows. Although register windowing can reduce the time it takes to process the function calls made by most programs, it incurs an overhead in terms of the amount of space that the registers take up. Superscalar RISC processors demand a large number of read and write ports because of the number of register accesses that will be needed each cycle, particularly as each instruction references up to three different registers.

One way to implement register windows is to give each register the same number of read and write ports and simply shift the window on each function call by changing a pointer. This has the downside of demanding a lot of space.

Doing a seven-ported design for 160 registers was going to be difficult. "It would have meant a lot of wire congestion," said Sun senior engineer Dale Greenley.

Chris Edwards is editor of Embedded Systems, and a contributing editor to Electronics Times, both sister publications to EE Times.