The companies' three-year C-language partnership will focus on hardware/software co-design, co-verification and performance analysis for complex system-on-chip designs. It will produce tools that will first be used in pilot projects, and then released to STMicroelectronics' design teams and customers, the companies said.

"We've been using C for system-level design for many years," said Pierre Paulin, director of embedded systems technology for STM. Every STM design group has created its own flavor of C, along with utilities and schedulers, and Paulin said the time has come for some corporate-wide standardization.

"Our R&D is talking to their R&D, which is closing the feedback loop," said Yankin Tanurhan, manager of system-level design partnerships at Synopsys. "This is certainly a big help for us."

To begin, the two companies are working on a way to specify systems independently of the final implementation. Both will leverage the SystemC C++ modeling platform as a way of doing so. A second effort involves performance evaluation for platform-based systems-on-chip in such areas as wireless communications and set-top boxes. Such devices use a predefined architectural structure to allow rapid creation of derivatives.

Further downstream, the two companies are working on hardware implementation, using technology developed by Synopsys and the University of Aachen (Germany) that helps convert floating-point descriptions into fixed-point designs. This technology was used in the pilot project that resulted in the recent Zipper-VDSL offering from STMicroelectronics and Telia Research.

On the software side, STM will integrate its own C-language DSP compilers with this Synopsys floating-point technology. A final area of research will be hardware synthesis directly from SystemC.

Quartet planned

On the design reuse side, a separate partnership will team Synopsys with STMicroelectronics to build what the companies are calling a "design reuse tool platform." Specifically, this effort will result in a tool called Quartet that will be targeted at STM first, but is expected to lay the foundation for a commercial offering.

Norm Kelly, senior marketing manager for design reuse services at Synopsys, said Quartet will fulfill four basic functions: IP generation, certification, packaging and instantiation. The "certification" part includes compliance to the design-for-reuse rules in STMicroelectronics' so-called Blue Book.

As such, Quartet will provide a function that is being increasingly referred to as "socketization." It will compete with the QuickUse Development System introduced by Mentor Graphics Corp. at last June's Design Automation Conference.

While Quartet will build upon Synopsys' existing coreBuilder product, it will go well beyond it, Kelly said. CoreBuilder today primarily focuses on the "packaging" part of IP creation, and is aimed at soft cores. Quartet, in contrast, will work with soft, firm and hard IP blocks.

"Making things reusable requires following different kinds of rules than people have followed in the past," said Kelly. "People have to have a tool base to do that."