The defense had argued that the industry needed more time to develop schemes that satisfy the needs of both hardware and software designers

"Judge" Daniel Gajski, a professor at the University of California, Irvine, who moderated the panel session/mock trial, sentenced EDA vendors to design million-gate ICs either manually or with their own behavioral-level languages.

Prosecutors persuaded a slim, 36-32 majority of attendees to convict. Motorola's Arkady Horak, IBM's William Lee, Philips Research's Kees Vissers and Toshiba's Michael Franz argued for the prosecution.

Horak said EDA CAD tools have caused him "countless hours of engineering frustration" over the course of his 15-year career as a systems engineer.

"System design is a very broad and hard-to-define problem," he said. "We have engineers in communication, transportation, networking, [and] computer areas that all have different needs, and some day we want to be able to share IP across all these groups. Today EDA vendors only provide some pieces of the system-level design puzzle."

Crimes of omission

Horak and his fellow prosecutors agreed that a lack of EDA-tool interoperability and an undefined top-down system-level design approach are the two main hindrances to system-level design. He said the programming language paradigms to capture specifications for systems designs fall short of satisfying the needs of all system designers. "We don't see industry initiatives like Open SystemC as a solution," said Horak. "I think a product database philosophy really must be adopted to fully realize the system-level specification."

Vissers said the EDA industry has yet to provide a solution that will allow his designers to perform a stepwise operation to generate testbenches at system level and reuse them down through RTL and physical-design levels. "We also need higher levels of abstraction, architecture exploration, reuse and support for configurable hardware," said Vissers.

Lee, a 14-year ASIC veteran who is doing complex system-on-chip designs, said that with IBM's capacity now reaching 35 million gates, the only way to complete chips on time is to practice design reuse. "Because EDA companies have not provided us tools that allow us to match our productivity to our capacity increases, our only recourse is to go with design reuse."

Lee noted the EDA industry is still struggling with providing hardware-verification tools. "You can buy a room full of event-driven simulators, keep 'em cool and pay all those license fees on an annual basis. You can also go with emulation. These large, expensive systems do work. However, in most cases, because of bring-up times, we found that there is almost no value for a first-pass architecture. You have to wait until the hardware stabilizes and the tools associated with the emulator are understood. It doesn't help with first-time silicon."

Lee said model-checking technology is still largely in the research phase and lacks the capacity for SoC designs.Franz said the EDA industry must develop tools that speed design-for-reuse. "My experience is that designing a block for reuse is about 2x to 7x the regular design effort," he said. "Design processes are different, documentation is extensive and testbenches and synthesis scripts need to be different."

In defending the EDA industry, Synopsys' Yankin Tanharan, Cadence's Grant Martin and Vast Systems' Graham Hellstrand argued that EDA is developing solutions for system-level IC design. "The main problem is that hardware and software engineers are two very different groups of people that in the past have not worked together," said Hellstrand. The EDA community, he contended, now has to bridge the gap and create a common language and solution so both groups can work together. That environment, according to the defense team, takes time to develop.

Implementation tools

Tanharan said that while the EDA industry has created software and hardware performance evaluation tools, it is just developing implementation tools that take hardware and software functional models and synthesize them to lower levels of abstraction. "Synopsys is delivering some of these tools today to our dedicated partners," said Tanharan.

Martin said Cadence is also developing system-level implementation tools through its Felix Initiative, but after three-plus years of development those tools are still not in the market.

"We need to work with the system-level design community to develop solutions," said Martin. "This not the beginning of the end, but we might see it as the end of the beginning."