Developed at the University of California, Irvine, SpecC promises to let engineers take an informal specification defined in one's natural language, like English or Japanese, and convert it into a formal, executable specification that can be simulated early. The idea is to streamline system definition by removing the miscues, misinterpretations and miscommunications among different design divisions.

Toshiba Corp., which is leading the drive and has helped sponsor the research, estimates that SpecC can halve the time it takes to come up with a spec and ready it for register transfer level (RTL) synthesis.

"The problem with defining the spec in one's [natural] language is that each engineer has a different idea of what they need to do," said Tadatoshi Ishii, a specialist in Toshiba's strategic intellectual-property (IP) group. "And each person believes he is doing the correct work."

Recently, standards bodies and EDA companies have lobbed a number of proposals backing the adoption of some form of C or C++, or extensions to Verilog or VHDL, as a so-called system-level development language. SpecC would add another language that sits sits on top of these variations of C or HDLs.

Toshiba executives said they and the 23 other companies backing SpecC — including Fujitsu, Hitachi, Matsushita, Mitsubishi, NEC and Sony — are not attempting to shove aside such proposals as SystemC from Synopsys Inc. and CoWare Inc., or CynApps, endorsed by Cadence Design Systems Inc. and Mentor Graphics Corp. Rather, they envision those languages eventually having an interface to SpecC.

"We believe it's complementary and we should cooperate," said Shojiro Mori, manager of Toshiba's strategic IP group, who said Toshiba is considering joining the SystemC consortium. "SpecC does not exist in SystemC. On the other hand, SystemC can cover SpecC."

SpecC would define the basic constraints of the system, such as power, performance and cost. Languages in the following steps would cover more hardware-specific issues. For that reason, SpecC should work in concert with other C-language schemes, backers say, and should not disrupt the rest of the design flow.

"VHDL and Verilog and C or C++ are languages for implementation," Mori said. "We also have to have a language suitable for spec description."

No threat

It's vital that SpecC is not viewed as a threat to SystemC in particular, because getting the support of Synopsys, which holds the dominant position in RTL synthesis, is essential "as far as end users are concerned," Mori said. He said one of the group's first tasks is to get Synopsys on board, and then other EDA vendors such as Mentor and Cadence. But since the consortium is so new, many companies haven't had time to evaluate the proposal. Synopsys did not respond to EE Times' questions about SpecC by press time.

Reaction to SpecC from other corners of the EDA world was mixed. "SpecC is yet another form of C strapped down with restrictions," said Simon Davidmann, chief executive officer of Co-Design Automation Inc. (San Jose, Calif.), which has been promoting its own Superlog language for hardware and system design. "What is good is that more companies realize that they have to move up from RTL, which is becoming the assembler language of system-on-chip design. But we don't believe this [SpecC] is the answer."

Davidmann also warned against fragmentation. "With so many C initiatives and languages around there's a real danger of different geographies going off in different directions," he said.

However, Steve Shulz, president of VHDL International, who said he is familiar with SpecC, said it could be one of several system-level development languages that could be integrated with the Rosetta language that his group is promoting. "[SpecC] is not that different from System C, except that it provides a better means for encapsulation and reuse/synthesis for communication across IP blocks," Shulz said.

John Sanguinetti, president of CynApps Inc., whose own open-source C++ class library has been endorsed by Cadence and Mentor, said that "the formation of the SpecC consortium is yet another indication that the EDA industry is moving in the direction of C/C++ as the language of specifying higher levels of design. The fact that two members of SystemC's steering committee [Fujitsu and Sony] are participating also indicates that the industry has not yet consolidated on a standard."

Aside from synthesis tools, SpecC will need support from compilers and from simulation, performance and estimation tools, said Toshiba's Ishii. "We need some cooperation for each tool, otherwise users will be confused when converting data from one to another," he said.

SpecC has been endorsed by embedded software developers such as Green Hills Software Inc. and Gaio Technology Co. Ltd. That support will help to cover the software design, since usually one vendor covers the entire design flow. Hardware design from the RTL down, however, involves more specialized companies, Ishii said.

While the SpecC language is well-defined, backers said opening it up to the design community was necessary in order to come up with a methodology because so many steps of the upper design flow — including planning, specification, behavioral modeling, and hardware and software design — need hooks to the language.

To generate support, SpecC is being offered for free. And though Toshiba engineer Kiichiro Tamaru is now chairman of the consortium, Toshiba executives said they are willing to let a third party, like an academic group, take over. Eventually they hope to submit the language to the International Standards Organization.

And though the group is heavily weighted by Japanese companies, Toshiba officials said they will reach out to companies in Europe and the United States as well. "Since we have just started, we have not invited all companies that would have an interest in this activity," said Ishii, especially overseas companies.

Yet this is not a case of U.S. companies being unaware of what's in their own backyard. The brainchild of UC Irvine's Daniel D. Gajski, SpecC has been in the works for 10 years under the sponsorship of companies like Hitachi, Motorola and Rockwell as well as Toshiba.

Case study

In fact, Motorola has commissioned UC Irvine to design a chip using the SpecC methodology. In a project that started in June 1998, the information and computer science department devised a voice encoder/decoder for a European GSM phone for Motorola's Semiconductor Products Sector to demonstrate the methodology. The design started from the abstract executable specification written in SpecC so that designers could explore different design alternatives before mapping the final software code and RTL hardware descriptions for synthesis, according a report on the project published last May.

According to the report, SpecC was used to define an IP-centric co-design methodology for the specification, modeling and design at the system level; a language based on ANSI-C, with explicit support for behavioral and structural hierarchy, concurrency, state transitions, timing and exception handling; and a CAD environment encompassing compiler, estimation and synthesis tools. Implementation details were left out of the picture.

Under SpecC, system designers defined their desired functionality and performance constraints in an executable specification. In this exploratory phase, designers looked at the number and types of system components, such as processors, ASICs and buses, and the partitioning among these and other elements. Scheduling was employed to determine the order of execution, the report said. A graphical user interface and automatic synthesis were used when making design decisions.

The synthesis flow was then handed off to the back-end tools. Hardware and software code is generated automatically. The software portion of the hand-off model is in C, while the hardware can be in either behavioral VHDL or C. The software C code is then compiled for the specified processor, and a high-level synthesis tool maps the functionality to custom hardware and the interfaces that connect the various processors, memories and IP.

One of the key advantages, say supporters, is that SpecC is a homogenous design environment. There are no translations to new languages during each step, and no mishmash of design representation at various stages.

Without introducing specific implementation details, SpecC aims to model the system at a very abstract level. Besides separating the communication and computation functionality, this includes designing in parallelism at the earliest stages; grouping related functionality under a hierarchical scheme; choosing the granularity of the basic parts; and modeling computation steps using state transitions, according the report.

— Additional reporting by Peter Clarke and Yoshiko Hara