EtherDesign was founded by Jeff Sutton, a former engineer at wireless networking firm Proxim (Mountain View, Calif.), now vice president of engineering for EtherDesign. Sutton said that his goal is to provide an easier way for communications engineers to run system-level simulations and do ASIC and FPGA design.

"All communications engineers are doing system-level simulation," Sutton said. "Typically they're doing things in Matlab, and they'd love to press a button and see hardware pop out. That's exactly what I'm trying to do."

Sutton said he's aiming his efforts at "guys who probably don't live and breathe hardware design, but would like to get into it instead of handing off designs." For these designers, most of whom already use C, Sutton believes his company's C-language based HDL is far more intuitive and easier to use than Verilog.

Sutton has essentially created a proprietary version of C, with added functions and operators to represent hardware concepts such as concurrency. "My C is designed for parallel hardware," he said. "It's very much like Verilog. You can't take my input and crank it through a C program."

Designers who use C2HDL today will essentially be working at the register-transfer level. But Sutton does plan to add higher-level state-machine support later. Instead of offering a behavioral-synthesis capability, EtherDesign is doing a straight translation of RTL-based C into synthesizable Verilog.

"When you write the code, you know exactly what you're going to get," Sutton said. "In fact, you can go in and figure out the exact number of gates that are going to show up in your design."

Output files

One of the C2HDL translator's outputs is synthesizable Verilog. But Sutton said he has so far tested it only with synthesis tools from Synplicity, not from Synopsys. The other output is a simulatable Matlab file that's cycle-by-cycle accurate compared with the Verilog file.

Thus, Sutton said, a designer can write a single C2HDL file to describe hardware, rather than write a C model for Matlab and then rewriting the model in Verilog.

To describe a parallel flow of actions, C2HDL introduces a new data type called "clock" and a new statement called "clocked if." Anything lying within a "clocked if" loop will be implemented as a register. "The nice thing is that you know when registers are going to show up," said Sutton. "You don't have a mystery."

Another difference between C and C2HDL is the parameter list of a function. The "*" operator is used in the parameter list to denote an output, whereas an input/output parameter, such as might be used for a bidirectional bus, is denoted with an "&" operator.

In the C output, all registers are made global, so they can be updated anywhere in the C program. A special function called "cycleWires()" propagates signals down wires after the processing for one clock cycle is performed.

C2HDL is available now for $4,000. A fully functional, four-month trial version is available for download from the EtherDesign Web site.