"We have a strategy," said Glenn Henry, who heads the Centaur design group. "It's very basic, but we think it is the right one to go after the low end," he said.

With speed and low cost in its sights, Centaur plans a processor "with a 12-stage pipeline and we are looking at taping out another with an 18-stage pipeline, so we will be gunning for megahertz," Henry said in a panel session at the Microprocessor Forum here. Henry's mention of the 18-stage pipeline device drew audible gasps from the crowd.

"You don't get as much extra performance as megahertz with such a long pipeline, but this is a megahertz game," he said. "We will get a 40-to-50 percent megahertz improvement with this pipeline, which is something people will really notice."

Each processor will fit into a 50 square millimeter die, issue just one instruction per clock cycle and support 133-MHz SDRAM. One chip will use a 128-kbyte L1 cache; the other will pack 192 kbytes. The processors are expected to sell for as little as $30 in quantity.

Centaur's standalone processors will be closely tied to the core logic of parent Via. Centaur is crafting a high speed (200 MHz or less) proprietary link between the processor and a north bridge memory controller. To speed traffic, the company will use a highly simplified version of the Socket 370 protocol over the interconnect. Centaur has no plans for proprietary links to any graphics controllers.

"Our approach is we don't spend any silicon to get one or two more instructions out per clock cycle because most of the time the processor is waiting on the bus anyway," Henry said. "Instead we spend our transistor budget creating deep write back buffers, store and fetch buffers and so on trying to free up the memory subsystem."

To date, Via has kept the Centaur design group of about 60 people intact in Austin, Texas, but it slashed back a 300-plus person Cyrix design team to about 80 people in Richardson, Texas. The two groups are generally pursuing their original road maps. Efforts to reconcile their product plans were delayed by the recent earthquake in Taiwan where Via is based.

For its part, sources said the Cyrix team, which currently lacks a leader, is focused on finishing its Gobi processor, now renamed Joshua.

"Via might give the processors from both teams a common brand so they seems to come from one family," said Linley Gwennap, principal consultant with MicroDesign Resources, host of the Forum. "Getting to integrated chips will take them a much longer time," he said.

Via could be behind the eight-ball in terms of integration if Intel follows through with reported plans to deliver its so-called Timna chip, a CPU combined with memory and graphics controllers. The chip is said to use an integrated Direct Rambus memory controller and has a target release date of late next year.

"It's hard for me to see Via integrating all these products and doing something faster than Intel with Timna," said Gwennap. "However, from what I heard Intel may not use Rambus in Timna, but instead do something much more like a merged Celeron processor and Whitney chip set."