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Japan embraces C for high-level chip designs








EE Times


TOKYO — The use of C for high-level chip design is gaining rapid momentum in Japan, where companies are seeking ways to churn out devices for consumer-electronics gear more quickly. The movement has resulted in some interest here in the Open SystemC initiative announced today by a Synopsys-led coalition.

Companies that have already started using C-level design include Fujitsu, NEC, Sharp and Sony. Of those, Fujitsu and Sony are listed as steering-group members for the Open SystemC initiative, which seeks to provide a standardized C++ "modeling platform."

"The main incentive [for using C] is that people doing system design architecture are doing it at a level above the current hardware description language, and doing it in C or C++. The problem is how to propagate that into chip- or board-level design," said Bill Baker, manager of engineering for Nihon Synopsys Co. Ltd. (Tokyo).

Hiroshi Nonoshita, senior engineer at the SoC Design Center for Canon Inc., said his company's engineering team is now exploring ways it can put C to use and said it would consider the proposal from Synopsys. Canon now consults with Synopsys for IP-related issues, he said.

"We are interested," Nonoshita said. "Some of our engineers have been trained for some of these types of tools, and we ourselves are now investigating them."

Aside from the promise of faster simulation, the move to C could help Canon's design teams quickly nail down specifications. "If we can write the spec with C, we can partition software and hardware interactively, and we can look at performance versus cost according to such partitioning and evaluate whether it should be done in hardware or software," he said.

NEC taps C

NEC Corp., for its part, is making greater use of C and will employ the language in the latest version of its internally developed OpenCAD6, which is expected to go into use this fall.

"In many cases, customers want to use software rather than hardware because software is useful for debugging and making modifications," said Katsuya Furuki, project manager for NEC's system ASIC Division, in a June interview. "Using C modeling, customers can do codesign, they can run simulation and check trade-offs of hardware and software."

But C lacks an inherent way to represent hardware concepts such as concurrency and parallelism. A C++ class library, such as that proposed by Synopsys, can overcome that deficiency.

In a separate research effort, NEC is attempting to alleviate some of the weaknesses of C language as a replacement for Verilog or VHDL by coming up with its own extensions to the language. Last year, the company announced Cyber, a C-based language for behavioral synthesis design intended to speed the development of logic circuits.











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