While a large number of electronic designs start with C or C++ modeling, there's never been an easy way to turn these models into synthesizable HDL, said John Sanguinetti, CynApps president and chief executive officer. The company's CynApps Suite promises to automate that transition, allowing designers to stay completely with C++ if they choose.

"Currently, you start with an architectural model in C or C++ and you have to rewrite it in Verilog to synthesize it. We need to make that an automatic process," Sanguinetti said.

CynApps is one of a number of companies advocating a new approach to high-level design. These include Co-Design Automation Inc., with its Superlog language; C Level Design Inc., which offers C-to-HDL translation; and LavaLogic, which is promoting Java as a next-generation design language. But CynApps feels that C++, with class libraries, is clearly the way to go.

"Neither C nor C++ by itself is adequate," said Sanguinetti. "You don't have a concurrency model or accurate data types. But C++ has the class notion, you can overload operators and you can extend the language in a well-defined way. C doesn't have that, so you have to do it outside the language."

CynApps, for instance, uses a C++ class template to allow hardware data types. Concurrency is expressed through C++ classes. Finally, the class library lets users describe ports, wires and reactivity, concepts that are missing from standard C++.

It's important to note, however, that the first release of the CynApps Suite does not provide a behavioral synthesis capability. It doesn't offer scheduling or resource allocation, which means that the C++ code it translates must already be fully elaborated, and be bit and cycle accurate. CynApps plans to add such features as scheduling and resource allocation in the future.

Further, the CynApps Suite is specifically aimed at hardware design, not system-level design, but this also is a likely future direction, Sanguinetti said.

The primary tool in the suite is Cynthesizer, which translates the bit and cycle-accurate C++ code into synthesizable Verilog. Typically, Sanguinetti said, it will be used after the designer has done some modeling and cycle-accurate simulation in CynLib.

"We're taking the position that what comes out of the synthesizer is comparable to assembly language," Sanguinetti said. "You can read and understand it, but you don't have to look at it or modify it. If you want to fix bugs or improve performance, you can do it all at the C++ level."

Testbenches can also be written in C++, he noted, and a CynLib testbench can even work with a Verilog model through the programming language interface (PLI).

The CynApps Suite lets users go the other way with Cynchronizer, a Verilog-to-C++ translator. It's provided as a way of dealing with legacy Verilog code, Sanguinetti said, and it provides an efficient alternative to co-simulation.

Cyn++ is a Verilog-like macro language that works with CynLib. With constructs such as "module," "initial," "always" and "posedge," it lets users write a more Verilog-like version of C++.

The fourth component of the CynApps Suite is Cyntax, a C++ lint tool that has an awareness of the CynLib class library. It detects a variety of syntax errors.

The CynApps Suite is available now for Unix and Linux platforms at a base price of $100,000.