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Analysis: 64-bit rivals set to take on Merced








EE Times


PALM SPRINGS, Calif. — The microprocessors that will drive the next generation of 64-bit computing — from Intel, Apple and Sun Microsystems — moved off the starting blocks and rolled toward the marketplace this week, sparking a rush of competitive jockeying in an industry segment that lately has been marked more by promises than by shipping processors.

Also firmly in the mix is Compaq, which is quietly preparing its powerful, next-generation Alpha. High-end spins of Hewlett-Packard's PA and Silicon Graphics' MIPS processor are in the works as well, although both companies have committed themselves to the IA-64 architecture, jointly developed by Intel and HP, for the long haul.

Intel, pacing the pack, demonstrated its initial working samples of Merced silicon here this week at the Intel Developer Forum. The 64-bit Merced is the first implementation of the IA-64 architecture.

Separately, at the Seybold Publishing Conference in San Francisco, Apple Computer Inc. interim chief executive Steve Jobs unveiled the long-awaited G4 family of PowerPC chips. Jobs claimed that a 500-MHz PowerPC G4 could outpace a 600-MHz Pentium III.

For its part, Sun Microsystems Inc. — likely Intel's most potent rival at the high end — said it has samples of its Ultrasparc III in hand and is on target for volume shipment in December.

The Merced announcement put to rest industry scuttlebutt that Intel was having trouble finishing the device on schedule. Such talk was fueled when Intel pushed back its self-imposed delivery timetable last year.

"We had some concerns a year ago when the replan [Merced pushback] was done," said Ralph Hedberg, vice president of marketing at Sequent Computer Systems. (Sequent has been purchased by IBM, but the acquisition won't be completed for another few months.) "But since then, Intel has met every milestone, and our confidence has been growing."

Now that Merced has made its appearance, however, the competitive landscape may have actually become more of a minefield, according to some analysts. "There's a lot more to making a business than having a good design," said analyst Janet Ramkissoon at Quadra Capital (New York). "This has become a very high-stakes power game. You have to have a lot of money and be able to manufacture what's designed.

"In other words, I can see a less elegant design winning," Ramkissoon continued. "In the end, although Sparc is a great architecture, I have a hard time seeing how enough volumes can be generated to see them through their road map over the next five years. As for Compaq, they still have to solve how to finance [Alpha] going forward and how they'll manufacture it. Samsung is [an Alpha] partner, and I believe they will be a real player going forward. However, will Alpha generate sufficient volumes to make it worthwhile?"

At this week's forum, Intel executives were positively giddy, showing off Merced samples, complete with L2 cache encased in a cartridge, to any and all onlookers. The cartridge has approximately 438 planar pins for the processor alone, as well as an edge connector devoted largely to power inputs. A solid metal bottom is included for heat sinking or fan-based cooling.

Intel officials compared Merced's performance bump over the Pentium III with the quantum leap in processing power that occurred in 1986, when the 80386 arrived and promptly upstaged the 286.

Intel president and CEO Craig Barrett kicked off the Merced-fest during his keynote speech, when he demonstrated a workstation platform, equipped with the processor, running Windows 2000 as well as Linux. (Windows 2000, previously referred to as Windows 5.0, is the upcoming version of Windows NT. It is not a full 64-bit OS, but rather a hybrid 32/64-bit offering.)

Still, Intel offered few details about the processor that weren't already publicly available.

When asked how fast the shipping silicon would be, one executive replied, "Fast enough." He noted that the first samples weren't "production speed, but they're also not the production stepping" that will hit the streets in mid-2000. Indeed, Intel expects to make a number of mask changes as it fixes early bugs during the next few months.

"We spent a lot of time on validation," said Gadi Singer, vice president and general manager of Intel's microprocessor group. To emphasize the point, and perhaps to exorcise the scourge of the notorious Pentium FDIV (floating-point) bug of 1994, Singer added, "We've validated it at the block level, chip level, with L2 cache, with the [core-logic] chip set and with software."

He noted that there are many "corner cases" — improbable but nevertheless possible occurrences — that must still be taken into account in testing. Fixes will be incorporated into the design before Merced goes into full production. "There will be mask changes before the production release," Singer said.

Another Intel official said Merced will be faster than the Pentium III, placing it in the 800-MHz ballpark.

Merced remains a code name; Intel said it has not yet decided on an official product name. As for cost, vice president of marketing Ron Curry said, "Merced will be priced consistent with the Xeon product line."

The current samples are being produced in a 0.18-micron process, on 8-inch wafers. "We have good yield," said Singer. "We have the quality of yield that we expected." He declined to specify the number of dice per wafer or the size of the chip itself.

Intel's Curry did say the company is "building [chips] in engineering sample volumes" of "hundreds [now], moving into thousands." Intel also confirmed another long-debated issue: Merced performs IA-32 compatibility in hardware, not software.

But one sore spot that nagged at the forum this week was which OEMs have already received samples of the processor. Both HP and Sequent declined to comment, citing their nondisclosure agreements with Intel.

Intel proved somewhat more voluble. "Not all our OEMs have samples [yet]," said Singer. "We are rolling it out. We have the OEMs come to our lab and they watch a system run, and then we give them a good cartridge."

The electrical and mechanical specs for Merced and its cartridge are still available only under nondisclosure, but Intel indicated that the spec may be made public in January, to foster the development of Linux-based systems around Merced.On the core-logic front, Intel will offer a commodity chip set, dubbed the 460GX, that will support up to four-way multiprocessing systems.

Many OEMs are designing proprietary core-logic sets to differentiate their systems. NEC is working on core logic to support eight-way and 16-way Merced machines. HP and IBM are also at work on separate, proprietary chip sets. Sequent, too, said that it is doing its own chip set, with an ultimate goal of supporting 64-way processing for a single operating-system image, and that it will continue the work once it becomes part of IBM.

On the board front, Intel will use Merced to drive its burgeoning board business forward with OEM — not branded — products. At the forum, the company showed a four-way server configuration code-named Lion. Also available will be a two-way workstation board set, code-named Big Sur.

Intel's successful debut of Merced this week prompted it to refute that the architecture is merely a placeholder for future, faster versions of IA64. "Merced is not a testbed," said Singer. "We have many OEMs planning real products with Merced." He also disputed industry reports that HP has taken the lead role in designing McKinley, the immediate successor to Merced, due in 2003. "McKinley is an Intel product," he said.

Nevertheless, Intel officials admitted McKinley will likely be a higher-volume product than Merced.

At the high end of the market in which Merced will play, Intel will have no more serious competitor than Sun Microsystems. The workstation maker, which maintains separate chip and systems business units, isn't buying Intel's new, upbeat take on Merced.

"We have 12,000 applications running on Sparc," said Fadi Azhari, marketing manager at Sun. "The issue for Merced is, Where are those applications? It's going to take a tremendous amount of time to get their apps tuned for optimum performance."

He also questioned which processor horse Intel was riding hardest. "I've been hearing them tell independent software vendors to go to McKinley. Now they're saying, [use] Merced."

One negative Sun will likely have to battle is the MHz question. Ultrasparc III is expected to debut at 600 MHz, a slower clock speed than Merced. But "MHz is not the only issue," said Azhari. "It's the scalability and the multiprocessing capability you can offer for the server market. We are 1,000-way MP capable, so from our perspective we're well ahead of the game."

While Merced and Ultrasparc III will play in the stratosphere of the workstation and server markets, much interest last week revolved around the San Francisco debut of the G4 PowerPC. Even though Apple's Jobs hyberbolically billed the G4 as a "supercomputer on a chip," analysts believe it is likely to be more of a niche product, given the company's traditional markets. Nevertheless, it will be a potent competitor in Internet servers.

Jobs' announcement was good news for Motorola, whose 128-bit AltiVec technology, rechristened the Velocity Engine, is present on all of Apple's G4 Power Macs.

Jobs also unveiled the silver-colored Power Macintosh G4 line of computers, equipped with a 22-inch flat-panel display. In Motorola's parlance, the G4 chip is really the MPC7400, a next-generation PowerPC chip. Fabricated on 0.15-micron design rules, it makes heavy use of copper interconnects.

The MPC7400 will be produced in 350-, 400-, 450- and 500-MHz varieties at first. All but the 500-MHz chip are sampling. Apple claims the Velocity Engine gives the G4 a sustainable performance of 1 Gflops and peak performance of 4 Gflops. Not to be counted out is what many architects consider the most elegant of all the 64-bit designs: Compaq's Alpha. The next-generation version, the EV-7 (or 21364), is scheduled to tape out in December. It's intended to support clock speeds in excess of 1 GHz and will include 1.5 Mbytes of integrated L2 cache, a 6-Gbyte/ second direct Rambus memory controller, a 3-Gbyte/s I/O interface and a direct processor-to-processor interface. The package is designed to support large-scale multiprocessing and high-availability systems.

Even with Alpha and Ultrasparc in the picture, Intel believes it has licked the one paper spec that has kept it from pushing to the front of the pack: floating-point performance. Merced will deliver 6 Gflops of single-precision floating-point and 3 Gflops double precision.

"The competition is on our minds," said Curry, "but we're not in a paper battle with them."











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