Simulation Magic will thus become another contender in the race to define a next-generation design language powerful enough for large system-on-chip (SoC) designs. Other recent approaches include Co-Design Automation's Superlog language, CynApps' C++ class libraries, LavaLogic's Java compiler and various companies offering C language tools and models.

One advantage Simulation Magic can claim is that its language was developed by a leading chip-design company to solve a pressing need. "We were burned a couple of times trying to build system-on-chip designs, so the company decided to develop some new technology," said Shay Ben-Chorin, president and chief executive officer of Simulation Magic.

Ben-Chorin, a 12-year veteran at National, moved over to that company's research lab to develop this new technology. The goal, he said, was to create a tool that could model complex systems in two weeks, using a graphical environment with embedded simulation knowledge.

National looked at existing commercial tools, Ben-Chorin said, but couldn't find anything that met its needs. He said hardware/software co-verification tools are too slow because they use HDL simulation to model the hardware portion of the design, and co-design tools don't make it easy to build models. "We wanted something fast that could help us build models really quickly," he said. "We couldn't find [that] in the market so we said, let's go do it."

The resulting Virtual Silicon product meets the project's goals, the company said. This high-level simulation environment includes Simulation Magic's C-based graphical language, code generators for C/C++ and Verilog, and processor models that run up to 25 Mips at the highest level of abstraction.

Simulation Magic, which employs 11 people, was incorporated in May to turn Virtual Silicon into a commercial product. Ben-Chorin said National has provided "seed money" but holds a minority share. Virtual Silicon release 1.2 is in use today inside National, but release 2.0, slated for beta testing in September and for production shipment around the end of 1999, will be the first version sold outside National.

Although the tools' approach can be used for any type of system-on-chip design, the new company will initially target wireless telecom, Ben-Chorin said. Inside National, Virtual Silicon has been used to model a GSM phone. Because the tool lets software developers run code quickly on top of a model of system hardware, it will be aimed primarily at software developers, Ben-Chorin said.

Virtual Silicon will come with processor simulation models that support three levels of abstraction. Cycle-accurate simulators are the slowest at 100,000 to 250,000 cycles/second. Functional simulators, which do not model the processor pipeline, run between 1 and 5 Mips. Ultrafast functional simulators, software programs that turn cross-complied code into native simulators, can run up to 25 Mips.

Simulation Magic currently has a functional Pentium-class X86 processor model and a cycle-accurate National CR16b RISC processor model, and is doing custom model development work. The company is working on integration packages for MIPS and ARM cores.

The rest of an SoC design is modeled with the graphical language, which generates C/C++ code that's linked to a simulation engine. Users can write cycle-accurate or functional code, and obtain over a million cycles or 1 Mips, Ben-Chorin said.

Virtual Silicon will also offer Verilog code generation as a way of connecting to downstream tools, and Simulation Magic hopes to forge alliances with EDA vendors, he said.

Besides heading up the new company, Ben-Chorin chairs the software subgroup of the Virtual Socket Interface alliance system-level design working group. That group is working to standardize an interface between instruction-set and system-level simulation. The hope, said Ben-Chorin, is that processor-core vendors will be able to write one instruction-set simulator that plugs into many environments.