The technology is the brainchild of TransModeling cofounders and EDA vets Steve Westfall, president and chief executive officer, and Chip Weeks Jr., vice president of sales and marketing. Dave Lowder is the company's vice president of engineering.

"When we decided to start a company, we thought about creating a transaction-based modeling tool," said Westfall. "We found there wasn't too much excitement for it. The people we spoke with said, 'That would be sort of interesting, but what we really need is something that will make simulation go as fast as it will possibly go.' That is what we developed in System Modeler."

Westfall claims the tool can generate extremely fast C++ models. "We did a benchmark with roughly 500-k gates, and . . . we were running 200 times faster than Synopsys VCX," he said. "We found that as the number of events goes up, the tool's models get faster — anywhere from 100 times to 1,000 times."

Westfall said any block in the system can be a System Modeler model, an HDL model or existing compiled code model.

The tool incorporates a block-diagram editor that describes a design's hierarchy, interfaces and connectivity. Users can generate C/C++ models from graphics, Verilog, VHDL or all three.

Transparent synchronization

System Modeler offers fine granularity with thread- and class-tree browsing and refinement. "Users can import third-party libraries, their own libraries and HDL code," said Westfall. Communication and synchronization between a distributed HDL simulation and the rest of the system model is said to be transparent.

The tool supports LSF by Platform Computing to provide load balancing across the user's compute farm, enhancing speed.

Such simulators as Cadence Verilog-XL, Synopsys VCS, and both Verilog and VHDL versions of Mentor Graphics' ModelSim are supported, as are the AR/T libraries and AR/T builder tools from Frontier Design.

System Modeler further supports Frontier Design's GSM and other cores and its Architectural Synthesis tool kit, which provides various application-specific units that can be defined in terms of behavior.

Westfall said the optional System Analysis tool will let engineers know when testing is complete and will help them determine which elements in the design hierarchy have problems.

The optional Model Packager, meanwhile, wraps HDL around C/C++ models, allowing for the distribution of high-speed models into the pure HDL execution environment. According to the company, Model Packager keeps the details of the model implementation hidden from the user of the model while maintaining any constraints placed on the model by the developer.

Any model within System Modeler, including the testbench, can be exported. The user determines whether packaged models are written as simulator-specific HDL wrappers, IEEE OMI-compliant models or pure C/C++ models.

Thus far, System Modeler is licensed through distributors only in North America. The company said it is interviewing distributors now for the Asian and European markets. The tool runs on Windows 95 and 98, Linux and HP platforms and lists for for $20,000. Upgrades offered as options will run in the $5,000 range.