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Hitachi researchers show new DRAM-like memory
Ron Wilson







EE Times


CAMBRIDGE, England — A team of researchers from Hitachi Ltd.'s Cambridge Research Lab and from Cambridge University have reported the development of a new type of memory cell that could potentially replace both DRAM and flash. The device, called a Phase-state Low Electron(hole)-number Drive Memory (PLEDM), offers the ideal combination of lower power than DRAM, faster read and write cycle times than DRAM, scalability to well beyond the levels where DRAM cells become problematic, fabrication with existing tools and techniques and — researchers have projected by not demonstrated — the ability to operate as a non-volatile memory. Hitachi believes the cell will be ready for production by the memory generation just beyond the 1-Gbit DRAM.

In the PLEDM, each bit of data is stored in a unique stacked structure, in which a small, uniquely designed transistor is fabricated over the gate of a larger, conventional MOS transistor. The PLEDM cell operates by sensing the state of about 1,000 electrons trapped between unique insulating barriers in the channel region of the upper transistor. These electrons are controlled by a side gate on the transistor, and their state in turn controls the gate of the larger transistor below, providing signal gain within the memory cell.

Hitachi said that the cell could be written in as little as 10 ns, allowing cycle times in the 100-ns range. Unlike conventional DRAMs, in which it becomes harder to store enough charge in the capacitor as the size of the cell decreases, the PLEDM cell is entirely scalable, and its performance should actually increase with smaller size, Hitachi sources said.

The researchers have demonstrated fabrication of the unique PLEDM transistor on oxide using a 0.2-micron process. Extrapolating from this transistor to a memory device, the researchers predicted that a multi-gigabit memory could be built with a sub-100-ns cycle time. In addition, they believe the structure of the barriers in the transistor's channel could be changed to make a non-volatile, rather than a dynamic, memory cell with similar performance and area and essentially infinite read/write endurance.











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