At last week's National Association of Broadcasters convention, Fujitsu vowed to make an aggressive push in the DTV market. The company will pursue slots for both ASICs and application-specific standard products (ASSPs) by leveraging the macro-based function blocks used in its high-definition decoder.

Only a handful of semiconductor companies currently offer complete DTV chip-set solutions. Fujitsu said its pricing will undercut those of competing solutions.

The company's DTV chip set for the U.S. market will include a high-definition MPEG-2 decoder, an 8VSB (vestigial sideband) demodulator and a separate AC-3 Dolby Digital decoder running on a homegrown 32-bit digital signal processor.

For Japan's digital satellite broadcast market, Fujitsu is spinning a baseband demodulator, high-definition video decoder and separate audio decoder. The audio chip, based on a proprietary 20-bit DSP, will handle MPEG-2 Advanced Audio Codec (AAC) decode, as mandated by the Japanese digital broadcast TV standard.

Fujitsu hopes to develop a single-chip DTV solution — integrating an high-definition decoder, DSP, CPU and embedded DRAM — by late next year or early 2001, according to Ali Erdengiz, Infor-tainment director at Fujitsu Microelectronics (San Jose, Calif.). The CPU core will most likely be a Sparclite, Erdengiz said.

Fujitsu will launch the MB86374 MPEG-2 Main Profile@High Level video decoder this summer priced at less than $50. The companion 8VSB demodulator, the MB87L3030, will be available at $20 in minimum lots of 1,000.

The MPEG-2 HD decoder incorporates a transport stream demultiplexer; an MPEG-2 video decoder; a video-output-format converter; and a 256-color, 1,920 x 1,280 on-screen-display. The chip, designed to support an 80-Mbit/second maximum input-bit rate, handles all Advanced Television Systems Committee (ATSC) formats plus the 1,440 x 1,080 format. The chip can decode and display one high-definition program or four standard-definition programs simultaneously. The on-chip format converter produces 1080i, 720p, 480i or 480p outputs while performing MPEG video scaling to arbitrary sizes.

The chip also comes with a memory-controller interface to two external 64-Mbit DRAMs. The chip is manufactured with a 0.25-micron CMOS process.

The decoder is hardwired silicon but is designed with a new, macro-based architecture, according to Fujitsu. Such blocks as format converters, datacast-support functions and graphics processing for customized GUIs can easily be put together in one ASIC, the company said.

Integrated VSB

The 8VSB demodulator, set to sample in June, is a fully in-tegrated chip with a front-end 10-bit analog/digital converter, demodulator and forward error correction, according to Erdengiz. The device accepts direct IF sampling at 44 MHz and thereby eliminates an additional down-conversion stage. Manufactured with a 0.35-micron technology, it complies with the ATSC standard for U.S. digital terrestrial TV receivers.

Erdengiz said the 32-bit DSP for Dolby Digital will be available in May and the AC-3 firmware will be available in June.