PALM SPRINGS, Calif. — Intel Corp. said its Merced processor development effort has reached a significant milestone: the running of the Unix operating system in a software simulation of a four-way Merced implementation.

The successful interoperability of multiple logic models of Merced opens the door for a full-scale push to finish the physical implementation of Merced in time for sampling to OEMs by the middle of this year, Gadi Singer, an Intel vice president who co-manages the Merced development effort, said at the Intel Developers Forum here.

System OEMs are receiving the simulation engines for Merced now, along with Spice and timing models, so they can debug software concurrently with the chip layout work being done by the hardware team. Besides the seven operating systems that are running on the Merced simulation platform, Merced marketing manager Ron Curry said Intel plans to work to bring up the Linux OS on Merced soon.

Curry said Intel will work with the Linux coordinating council. "The open-source model needs to continue to evolve," Curry said, adding that Intel's view is that technology needs to be developed and tested by companies first, and then shared with the larger community. Some individuals "with a holier-than-thou" mentality argue that innovations should be shared as they are conceived and being worked on.

Singer, and Merced program co-manager Stephen Smith, told reporters that the Intel 460GX chip set, which will support four-way Merced processing, is taping out now. Other system OEMs outside of Intel are developing chip sets that will support 8-way and higher levels of multiprocessing.

Intel said Merced would achieve 3-Gflops extended-precision floating-point performance and 6-Gflops single-precision performance. "Those two numbers were enough to convince some of my users we made the right move in going with Merced," crowed John Mashey, director of systems technology at Silicon Graphics Inc. in a panel session here.

Intel promised that Merced would handle the RSA encryption algorithm twice as fast as any other processor now on the market, but kept mum about Merced performance details overall.

Singer, who ran Intel's corporate CAD effort until last summer when he was brought in to work with Smith, brought a sample of the Merced cartridge to IDF. Level zero and Level 1 cache are on-chip, but the cartridge will allow Level 2 cache to communicate across a full-speed bus to the processing elements. Besides the normal heat spreader and fan, Intel is investigating the use of a heat pipe to vector off thermal energy. The heat pipe is essentially a copper pipe with liquid sealed inside. The goal is to meet the thermal budget of customers, such as Internet service providers, which use rack-mounted servers in a confined space.

Also, Intel fellow John Crawford, and Hewlett-Packard senior architect Jerry Huck, described how the IA-64 architecture will take advantage of advances in the compiler and instruction set. Branch-specific static prediction, and predication techniques, will reduce mispredict penalties, while software pipelining will support the parallelism possible with Merced's multiple execution units, Crawford said.

The RISC processors now on the market have attempted to implement predication and software pipelining by using "cmove" and "non-faulting load" instructions, which Crawford said were attempts to "bolt on" technology to older architectures. Those older architectures use branch-prediction techniques, which mispredict about 5 to 10 percent of the time, resulting in performance penalties of 30 to 40 percent.

Crawford described "static branch prediction," in which the compiler predicts which branch is normally, or almost never, taken. That allows the hardware to concentrate more resources on difficult-to-predict branches. Also, parallel compares will dedicate hardware to inherently segment the compares, which reduces the critical path. A "queen's loop" function can be done in four cycles, rather than seven on the IA-32 architecture.

The IA-64 architecture will support data speculation, allowing the compiler to issue a load prior to store— which might introduce conflicts— and better exception handling, which defers the exception to the optimum time. Speculation will improve memory latency by 79 percent when combined with predication, important in servers that handle large databases with many accesses to cache, Crawford said.