SAN JOSE, Calif. — Programmable logic vendor DynaChip Corp. has produced a PCI core that executives say is the first to draw the full bandwidth potential out of the 66-MHz, 64-bit PCI bus.
The DynaCore PCI66, initially implemented on DynaChip's DY6055 FPGA, is a soft core that eliminates wait states, effectively doubling the speed of data that can be drawn off the bus. The part is being targeted at networking applications.
Most PCI chips for the 66-MHz, 64-bit bus include a wait state to compensate for chips that are unable to keep up with the bus speed. In particular, a 66-MHz PCI interface has certain paths that must meet a 3-ns delay. If a chip can't meet that spec, a wait state is introduced to move data through in two clock cycles instead of one. This halves the chip speed but increases the critical delay to 6 ns — "it buys them some extra time," said Eric Fleischman, vice president of marketing for DynaChip (Sunnyvale, Calif.).
Unfortunately, it also cuts the data throughput in half: to 264 Mbytes/second instead of the 528 possible. Taking advantage of its active-repeater FPGA architecture, which was designed for speed, DynaChip says it has eliminated this problem.
The core consumes one-third of the DY6055 chip, leaving 36,000 gates free for integrating back-end logic. That figure will increase to 86,000 when DynaChip introduces its 0.25-micron chip in the second quarter, Fleischman said.
DynaChip expects to ship the DynaCore PCI66 during the first quarter, charging a $5,000 multiuse licensing fee.
