Castle Networks Inc. will detail a system that will aim to mediate traffic between circuit- and packet-switching systems in telco central offices. And at the Next Generation Networks conference here, T.sqware Inc. today (Nov. 2) will disclose an architecture it says will blend key circuit- and packet-based functions in a single, 12-million-transistor processor.

The architectural gambits come hard on the heels of moves last week by Hewlett-Packard, Cisco Systems and Nortel Networks Inc. to define integrated systems that will speed the evolution of the wide-area network from a voice to a data highway. HP and Cisco will define a gateway controller for the telco central office. Nortel is consolidating voice-over-Internet Protocol and IP-access architectures for the WAN.

Castle Networks (Westford, Mass.), a startup formed by executives from Cascade Communications Inc., will provide a sneak peak at the architecture behind its Services Mediation Switch, which intends to link Class 5 circuit switches based on Signaling System 7 with high-speed IP switches and routers in telco central offices. The system is slated for beta test early next year.

At the chip level, T.sqware's TS704 Edge Processor combines four Sparc cores on a split-cycle on-chip bus to create a network processor that could power a variety of next-generation hybrid circuit/packet switches. First silicon has been achieved, and the company is ready to move into sampling of the 388-pin, 0.35-micron CMOS processor.

The various moves recognize the growing demand from carriers to unify packet and circuit traffic, though the players disagree on exactly how — and how fast — unification should occur.

"The circuit network of the past will go away, and how service providers will make the transition to packet networks will be critical," said Cisco chief executive John Chambers.

But Castle has sought to silence the calls to "throw away the circuit switch," said Tom Burkardt, chairman and president. A realistic model for carriers must assume the preservation of a circuit switch through a transition that could last years, in which the Castle Services Mediation Switch would act as mediating hardware between circuit and packet systems. That's the first step in Castle's view of a three-phase program to wean carriers off packets.

Move to SS7
A second phase — to be completed using emerging standards from the Internet Engineering Task Force and other bodies for standard IP/SS7 gateways — involves moving ATM and Internet Protocol signaling directly into SS7. Finally, Castle would help partners and service providers develop native apps for circuit and packet through application-programming interfaces that leverage both IP and telephony databases.

Castle has partitioned its architecture into four layers. The Access Processor connects line-side interfaces — such as analog phone lines, digital subscriber lines, wireless and coaxial cable — to a transport server that assigns such transmission-layer interfaces as time-division multiplexing, wavelength-division multiplexing, Internet Protocol, ATM and Sonet. To assign an abstract service between line-side and transport access, a universal signaling matrix binds signaling stacks, such as SS7, Q.2931 or H.323, to an end-user service.

The signaling matrix sends connection-setup requests to a Mediation Policy Engine, which allows a call to access telephony-oriented databases as well as IP-oriented databases.

Convergence on silicon
For its part, T.sqware today will unveil the architecture behind its Edge Processor, which it claims can handle circuit- and packet-processing functions, ranging from remote-access concentration to central-office broadband switching, for the WAN. The startup also will reveal a minority investment by Level One Communications Inc. (Sacramento, Calif.).

The 7XX Edge Processor CPUs are combined with adjunct chips, such as time-division muxes and demuxes, to allow the architecture's use in routers, packet switches, circuit switches and even Sonet add/drop multiplexers. T.sqware will target the range of veterans and startups developing hybrid circuit- and packet-switched solutions.

T.sqware opted for an on-chip split-cycle bus that combines an in-order instruction fetch with out-of-order execution. The fully interleaved memory-access subsystem lets each of the four on-chip Sparc/High-level Data Link Control processor blocks access memory at any time in the bus cycle. That was the only solution that allowed efficient handling of bursts for telecommunication systems that must optimize both control and data flows, said Alain Fanet, T.sqware president and chief operating officer.

T.sqware chairman and chief executive, Michel Desbard, said that in developing the company's business plan, the founders realized that network-equipment vendors would face three separate performance barriers between now and 2005: processor speeds, bus contention and memory access. A processor architecture that solved one problem without addressing others would have a short shelf life. T.sqware thus avoided a multichannel High-level Data Link Control microcontroller approach, instead turning to an out-of-order execution architecture based on multiple Sparclet cores to optimize both control and data flows simultaneously.

The 704's on-chip bus can act as a scalable switching fabric for large packet or hybrid switches, but a standalone Edge Processor also can be used in a remote-access router or Sonet add/drop mux to perform protocol encapsulation and QoS traffic management. For channelizing multiple DS-0 (64-kbit/second) lines, the 704 can be used with the TS518 TDM concentrator, also debuting this fall.

Suggesting that mapping of channelized DS-0 or T1 services will be an important feature, Desband said T.sqware has signed an agreement with Trillium Digital Systems Inc. (Los Angeles) to port several signaling-protocol stacks to the Edge Processor. When raw T3 channels are used, the processor can support three T3 channels, but when DS-0 or T1 channelization is used, the chip supports a single T3 (45-Mbit/s) pipe.

T.sqware does not bill itself as a high-layer (Layer 3 routing or Layer 4 transport) processor company, but instead sees HDLC Layer 2 data-link control as the basis for uniting WAN-access services. Fanet said IP and SS7 gateway functions are all moving to termination of calls at Layer 2.

Meanwhile, the split-cycle bus makes the processor preferable to multi-RISC core devices that retain traditional bus designs for HDLC calls. And the chip can handle higher-layer QoS functions for IP routing via effective control of buffer memory, according to T.sqware.

The 360-Mips TS704 can handle 155-Mbit/s speeds but lacks the overhead to accommodate a Sonet/ATM OC-3 line. For those services, T.sqware will introduce a TS7xx processor in 1999 with 400-Mips throughput and a 300-Mbit/s capability. For ATM/Sonet OC-12 (622 Mbits/s), T.sqware plans a processor in 2000 that will add IP routing functions.

Castle's Burkardt said that the TS704 has sampled too late to be used in Castle's first-generation systems and that Castle has not committed to using the architecture for future systems.