IP Selection: Part 2

As complex chip design has evolved from massive RTL synthesis toward integration of existing intellectual property cores, the selection of IP has become one of the most critical steps in the entire chip design process. Yet it is one of the least documented and least supported by tool vendors. Left to their own devices, design mangers must find sources for the IP they need, identify blocks with the right functionality and estimate their ability to integrate the blocks successfully into their design.

EETimes' IP Selection Industry Challenge attempts to support these design managers in their efforts. With a combination of field research and analysis, we will establish how design managers are going about IP selection today. We will match results with practices to estimate which are the most successful techniques for IP selection. And we will report on the direction in which the graduallydeveloping IP chain is moving. We hope the IP Selection Industry Challenge gives design managers a clear view of what their peers are doing in this vital area, and a basis for moving forward.

Net Seminar NetSeminar: How Designers Select IP Wednesday, December 14, 2005; 11:00 am PT/2:00 pm ET As complex chip design has evolved from massive RTL synthesis toward integration of existing intellectual property cores, the selection of IP has become one of the most critical steps in the entire chip design process. Yet it is one of the least documented and least supported by tool vendors. Left to their own devices, design mangers must find sources for the IP they need, identify blocks with the right functionality and estimate their ability to integrate the blocks successfully into their design. Join EE Times Semiconductor Editor Ron Wilson and a panel of industry experts as they review the results of a recent global Web questionnaire explaining how design managers are dealing with the IP selection problem today. Register here.