Data/event control and data processing still play a key role in many elements of the new computing environment in which we find ourselves. But where in earlier generations of computing, the I/O and data movement were in support of the processing of data and control of events, in many embedded networking environments exactly the reverse is true.

At whatever level you view things, at the chip level, board, system and the broader network environment, the key concern is with the movement of large amounts of data. As in all real world situations, it is not an either/or situation, event control and data processing on one side and to something totally untried, outside the university and reach environment, such as the impressive but still arcane data flow architecture, on the other. It will be something in between, or something totally new that serves the diverse needs of the new network-centric computing environment.

Contributors to this week's In Focus offer some unique perspectives on how the network infrastructure is weathering the shift. Even system-on-chip designers are affected, says contributor Scott Bowden, director of applications at Xyron Semiconductor Corp. (Vancouver, Wash.). SoC architects are finding that the nature of the data that must be handled in designs incorporating audio and video components demands they rethink their underlying design methodologies, shifting from one based on sequential event control to one based on data flows.

And the change affects more than methodology, according to contributor Robert Payne Sr., vice president and general manager of advanced system technology at Philips Semiconductors (San Jose, Calif.). It involves overhauling the underlying SoC architecture — at least in that segment of the market focused on devices for a variety of applications in home entertainment, wireless communications and personal computing. "The diverse range of media types and the bandwidth at which they are being fed into the small footprint consumer and appliance devices is presenting a challenge that is unprecedented," he said. "The volume of data that must be moved around a complex SoC is like nothing embedded designers have ever faced and it requires we rethink the basic architectural assumptions under which we have been operating."

In the current network infrastructure, this fundamental shift is already occurring. One example at the systems level is the shift, even within data processing oriented server farms, to new interconnect structures based on switch fabrics.

In servers, the shift from shared bus to serial switch fabrics has increased the throughput so much that the designer of an Internet Data Center now disaggregates many of the functions that were previously incorporated into a four-way CPU configuration, into dozens or hundreds of smaller server blades, said Gabriele Satori, president of the Hypertransport Consortium, which is competing with alternatives such as Infiniband and RapidIO in the fabric interconnect market. "Now the main problem facing designers is how to manage the much more complex I/O functionality and the data that flows between the blades at six to ten times the throughput of previous leading edge shared bus techniques," he said. "The switch fabric methodology that will win will be the one that can most easily allow developers to transition from the previous shared bus techniques based on PCI, cPCI and PCI-X, as well as manage the much more complex data flow environment they are in."

Best throughput, lowest rate

According to Rubin Dhillon, director of network business development at SBS Technologies, Inc., (Mansfield, Mass.), it is clear from the engineers that he has talked to that the issue of how to manage data flows is the paramount problem facing them, especially in the current economic environment where they want the best throughput they can get, but at the lowest cost and with the system architecture.

"Whereas in the past the primary focus has been on the performance and throughput of the main RISC engine in a design," he said, "many of the people we talk to are much more involved in I/O issues. " There is also much more interest in network processors, he said, where the debate seems to be between purely programmable NPU solutions that are much more in the data flow camp, such as the Intel IXP2800, which would require some degree of relearning and new tools, or wether to stick with solutions that depend more on traditional RISC engines aided by specialized ASICs for the data plane.

In his contribution, Gary Lidington, vice president of marketing at Xelerated, Inc., (Burlington, Mass.) discusses how the time has come to shift to a more purely data flow architecture, because traditional sequential RISC architectures have some fundamental limits in the networked environment. "Data flow architectures were first articulated in the late 1960's with prototypes built at several research institutions during the 80's and 90's," he said. "In contrast to control-centric von Neumann architectures , such as RISC, data flow architectures use the availability of data to fetch instructions rather than the availability of instructions to fetch data."

He point out that before the ubiquitous net-reification of computing, when applied to general purpose computing problems, pure data flow machines were deemed harder to program than more conventional architectures and therefore never found their way into mainstream computing systems. Less purely data flow configurations based on hybrids incorporating RISC engines into the management and control planes are now finding their way into high performance network processors.

"Because RISC architectures have not been designed from the beginning to run real time applications, they employ shared resources in their instruction pipelines, directly access shared external resources and often employ statistical speed-up features such as cache," said Lidington. "This translates to variable instruction execution times that tend to average out when running long programs, but become very noticeable when running short programs such as data path applications." This makes it difficult to predict performance and guarantee wire speed operation without extensive performance testing.

And although it may be possible to calculate a deterministic upper bound on program execution except in the case of multithreading, he said, it results in a requirement for extra headroom in the application that reduces the effective instruction budget which reduces both performance and efficiency."

Multi-service net wave

Also dictating a more hybrid approach to network processing is the increasingly complex nature of the switch and router environment, especially at the network edges, where range of services, quality of service, and cost are paramount. Pushing things in this direction are trends toward multi-service networking and a much more media rich and diverse network environment, especially as Voice over IP becomes more common, says contributor, Vinoj Kumar, product architecture manager, at Agere Systems, Inc., (Allentown, Penn.), and chairman, NPF Software Interface Task Group,

"Using one network for voice and data (and even video) has the potential for many advantages: the network resources can be used more efficiently, capital costs are lower, and operating expenses can be reduced," he said, "and multi-service networks are networks that can support multiple protocols simultaneously while providing the sophisticated traffic management capabilities required to give each service type the appropriate performance guarantees."

But unlike systems servicing single protocols, he noted that multi-service systems handling multiple data flows introduce new problems, foremost among them, Quality of Service (QoS). Acccording to Agere's Vinoj Kumar, QoS is a term that covers a lot of network issues — bandwidth (provisioning), classification (identifying which streams are a higher priority than others), and priority queuing and scheduling (being able to give properly identified streams the performance they demand). The challenge faced by network system designers using NPUs and switch fabrics, he said, is to implement QoS mechanisms that work well across various protocols and traffic types.

"Whatever architectural paradigm or paradigms that emerge at the chip, board, system and network level," said Philip's Payne, "one thing is certain, management of data flows, data streaming and I/O issues are the fundamental problems that computer designers, SoC architects and board developers are going to be facing for a number of years."